Patent
Nanotube transistor device
Reads0
Chats0
TLDR
In this paper, a transistor device comprising source and drain regions (S, D), a nanotube structure (2, 3) providing a path for electrical charge carriers between the source and Drain regions, and a gate region (4).Abstract:
A transistor device comprising source and drain regions (S, D), a nanotube structure (2, 3) providing a path for electrical charge carriers between the source and drain regions, and a gate region (4). The nanotube structure has its conduction band structure locally modified in the gate region, e.g. by doping, for controlling the passage of the charge carriers in the path. The device can be used as a flash memory or as a memory element in a DRAM.read more
Citations
More filters
Patent
Self-aligned process for nanotube/nanowire FETs
Phaedon Avouris,Roy A. Carruthers,Jia Chen,Christopher Detavernier,Christian Lavoie,Hon-Sum Philip Wong +5 more
TL;DR: In this article, a complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described.
Patent
Non-volatile memory device
TL;DR: A fin-FET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate.
Patent
Nanotube transistor and rectifying devices
Thomas W. Tombler,Brian Y. Lim +1 more
TL;DR: In this article, a single-walled carbon nanotube transistor and rectifying devices, and associated methods of making such devices include a porous structure for the single-Walled carbon Nanotubes, which may be anodized aluminum oxide or another material.
Patent
Carbon nanotube field effect transistor
Aaron A. Pesetski,Hong Zhang,John Adam,John X. Przybysz,Jim Murduck,Norman Goldstein,James E. Baumgardner +6 more
TL;DR: A carbon nanotube field effect transistor (CNEFET) as discussed by the authors is a CNEF with a gate dielectric and a gate electrode separated from the carbon-notube by the gate.
Patent
Fabrication of graphene nanoelectronic devices on SOI structures
Yu-Ming Lin,Jeng-Bang Yau +1 more
TL;DR: In this paper, a semiconductor-on-insulator structure and a method of forming the silicon on insulator structure including an integrated graphene layer are disclosed, and the method comprises processing a silicon material to form a buried oxide layer within the silicon material, a silicon substrate below the buried oxide, and a silicon-oninsulator layer on the ground oxide layer.
References
More filters
Patent
Field-effect transistor
TL;DR: In this paper, a field-effect transistor with an active layer and a gate insulating film is presented, where the active layer includes an amorphous oxide layer and the gate insulator.
Journal ArticleDOI
Metal–insulator–semiconductor electrostatics of carbon nanotubes
TL;DR: In this paper, the capacitance per tube is reduced due to the screening of the charge on the gate plane by the neighboring nanotubes, which provides the possibility to use C-V measurements to diagnose the electronic structures of nanotube.
Patent
Nanotube semiconductor devices and methods for making the same
TL;DR: In this article, the authors describe a vertical transistor/capacitor cell with a single nanotube, which is used to form the individual devices, including a single transistor and a capacitor.
Patent
Band-structure modulation of nano-structures in an electric field
TL;DR: In this article, a method to electronically modulate the energy gap and band-structure of semiconducting carbon nanotubes is proposed, which can be used in applications such as switches, transistors, photodetectors and polaron generation.
Patent
Molecular wire crossbar flash memory
James R. Eaton,Philip J. Kuekes +1 more
TL;DR: In this paper, a nano-scale flash memory is proposed, which comprises: (a) source and drain regions in a plurality of approximately parallel first wires, the first wires comprising a semiconductor material, the source and Drain regions separated by a channel region; (b) gate electrodes in an array of parallel second wires, with the second wires comprising either semiconductor materials or a metal, crossing at a non-zero angle over the channel regions, to form a array of nanoscale transistors; and (c) a hot electron trap region at each intersection of the