NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
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Citations
Access Regulation to Hot-Modules in Wormhole NoCs
Feature - NoC emulation: a tool and design flow for MPSoC
Design automation for application-specific on-chip interconnects
Bandwidth-Aware Application Mapping for NoC-Based MPSoCs
References
Computers and Intractability: A Guide to the Theory of NP-Completeness
Networks on chips: a new SoC paradigm
Route packets, not wires: on-chip interconnection networks
Reconfigurable computing: a survey of systems and software
Related Papers (5)
Frequently Asked Questions (17)
Q2. What is the core of the proposed design methodology?
A library of highly parameterized, design time composable network building blocks ( pipes) is at the core of the proposed design methodology.
Q3. What is the main tool used in the topology mapping phase?
NetChip in-turn has two tools built into it: SUNMAP which performs the topology mapping and selection phases and the pipesCompiler which generates the selected topology.
Q4. What is the reason for the large area savings achieved by the butterfly network?
The smaller number of switches and smaller switch sizes also account for the large area savings achieved by the butterfly network.
Q5. How did the authors validate the need for Clos networks?
The authors validated the need for Clos networks by producing mappings onto various topologies by relaxing the bandwidth constraints and simulating the resulting SystemC design.
Q6. What is the purpose of the debugging mode?
In order to automate tracing of signals, a debugging mode has been implemented, that enables monitoring of any signal in the design.
Q7. What are the early works in the literature on shared busses?
the early works in [2], [34] pointed out the need for more scalable architectures for on-chip communication and, therefore, to progressively replace shared busses with on-chip networks.
Q8. What is the fastest topology for a regular topology?
A regular topology, for example, such as a 16 16 mesh, can be generated faster than an irregular, application-specific topology with only few cores and switches.
Q9. What are the advanced state-of-the-art communication architectures?
The most advanced state-of-the-art SoC communication architectures represent evolutionary solutions with respect to sharedbusses.
Q10. What is the unused part of the datastream?
The unused part of the datastream is stored in a regpark register, so that a new datastream can be read from the HEADER_BUILDER block.
Q11. What is the function that stores flits?
module OUT_BUFFER stores flits to be sent across the network, and allows the NIS to keep preparing successive flits also when the network is congested.
Q12. What is the high-level description of the network?
The high-level description consists of the definition of the cores, network interfaces, switches, links, and their interconnections.
Q13. What is the average link length in the butterfly network?
The average link length in the butterfly network (obtained from floorplanner) was observed to be longer than the link lengths (around 1:5 ) of direct networks.
Q14. What is the smallest bounding box between the source and destination nodes?
For a torus network, the wraparound channels need to be considered for computing the smallest bounding box between the source and destination nodes (Fig. 2d).
Q15. What is the role of the network topology in the design of a NoC?
Setting up a fully automated synthesis framework for NoCs is a nontrivial task, particularly for the case of application specific MPSoCs, where a set of heterogeneous computing and storage resources have to be interconnected to each other by means of a custom-tailored communication network.
Q16. What is the maximum distance between adjacent switches halves?
The maximum distance between adjacent switches halves with each stage (e.g., switch 0 of stage 1 is connected to switches 0 and 2 of stage 2, resulting in a maximumdistance of 2.
Q17. What is the power dissipation for the switches and links?
Using the built-in power models, power dissipation for the switches and links are calculated based on the average traffic (shown as edge annotations in Fig. 2b) through them.