Journal ArticleDOI
On the fault coverage of gate delay fault detecting tests
A.K. Pramanick,Sudhakar M. Reddy +1 more
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TLDR
A new and more realistic delay model is proposed to obtain true fault coverages that extend up to the actual circuit slacks whenever possible and an alternate test application strategy, involving the usage of varying sampling times, is also proposed to further enhance the actual fault coverage obtained under the proposed delay model.Abstract:
This paper addresses the problem of obtaining accurate fault coverages for the gate delay fault model. For a gate delay fault, it is not sufficient to only find a test. One also has to accurately determine the size of the fault detected. We first show that previous methodologies for determining gate delay fault coverages have certain limitations. A method is then investigated to determine all the possible ranges of detected fault sizes, using the traditional fixed sampling time approach. However, with the constraints of a realistic inertial delay model, it is then shown that it might still not be possible to achieve the coverages required to guarantee circuit operation without malfunctions. A new and more realistic delay model is proposed to obtain true fault coverages that extend up to the actual circuit slacks whenever possible. An alternate test application strategy, involving the usage of varying sampling times, is also proposed to further enhance the actual fault coverages obtained under the proposed delay model. Results of experiments performed to evaluate these methods are given.read more
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VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
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VLSI Test Principles and Architectures: Design for Testability
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
Proceedings ArticleDOI
Defect-based delay testing of resistive vias-contacts a critical evaluation
TL;DR: In this paper, a defect-based study analyzes statistical signal delay properties and delay fault test pattern constraints in the CMOS deep submicron environment, where CMOS resistive vias and contacts were used as a delay defect target.
Proceedings ArticleDOI
TranGen: a SAT-based ATPG for path-oriented transition faults
TL;DR: A SAT-based ATPG tool targeting on a path-oriented transition fault model, utilizing an efficient false-path pruning technique to identify the longest sensitizable path through each fault site, which can be orders-of-magnitude faster than a commercial AtPG tool.
Proceedings ArticleDOI
A Simulator of Small-Delay Faults Caused by Resistive-Open Defects
Alejandro Czutro,Nicolas Houarche,P. Engelke,Ilia Polian,Mariane Comte,Michel Renovell,Bernd Becker +6 more
TL;DR: This work couple the calculation of the critical size of a small-delay fault with the computation of the resistance range of the corresponding resistive-open defect for which this size is exceeded, and is able to extend probabilistic fault coverage metrics initially developed for static resistive bridging faults to small- delay defects.
References
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Proceedings ArticleDOI
A logic design structure for LSI testability
TL;DR: A logic design method that will greatly simplify problems in testing, diagnostics, and field service for LSI is described, based on two concepts that are nearly independent but combine efficiently and effectively.
Proceedings Article
Model for Delay Faults Based Upon Paths
TL;DR: A procedure is described which identifies paths which are tested for path faults by a set of patterns, independent of the delays of any individual gate of the network, which is a global delay fault model.
Journal ArticleDOI
On Delay Fault Testing in Logic Circuits
Chin Jen Lin,Sudhakar M. Reddy +1 more
TL;DR: Algorithms, based on a five-valued logic system, to accurately calculate the detection probability of path delay faults by random delay tests as well as to derive deterministic tests to detect pathdelay faults are proposed.
Proceedings ArticleDOI
On the detection of delay faults
A.K. Pramanick,Sudhakar M. Reddy +1 more
TL;DR: An algorithm was devised and implemented to automate the process of test generation, and results of experimentation with the ATPG, as well as with a random-pattern simulator, on four ISCAS-85 circuits were reported.