Proceedings ArticleDOI
On thermal effects in deep sub-micron VLSI interconnects
Kaustav Banerjee,Amit Mehrotra,Alberto Sangiovanni-Vincentelli,Chenming Hu +3 more
- pp 885-891
TLDR
This paper presents a comprehensive analysis of the thermal effects in advanced high performance interconnect systems arising due to self-heating under various circuit conditions, including electrostatic discharge.Abstract:
This paper presents a comprehensive analysis of the thermal effects in advanced high performance interconnect systems arising due to self-heating under various circuit conditions, including electrostatic discharge. Technology (Cu, low-k etc.) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration reliability has been analyzed simultaneously, which will have important implications for providing robust and aggressive deep sub-micron interconnect design guidelines. Furthermore, the impact of these thermal effects on the design (driver sizing) and optimization of the interconnect length between repeaters at the upper-level signal lines are investigated.read more
Citations
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Journal ArticleDOI
3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration
TL;DR: This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design.
Journal ArticleDOI
Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods
Massoud Pedram,Shahin Nazarian +1 more
TL;DR: A brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power V LSI circuits is presented.
Proceedings ArticleDOI
A thermal-driven floorplanning algorithm for 3D ICs
Jason Cong,Jie Wei,Yan Zhang +2 more
TL;DR: A thermal-driven 3D floorplanning algorithm with CBA representation that can reduce the wirelength by 29% and reduce the maximum on-chip temperature by 56% is proposed.
Journal ArticleDOI
A power-optimal repeater insertion methodology for global interconnects in nanometer designs
Kaustav Banerjee,Amit Mehrotra +1 more
TL;DR: In this paper, a methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty, and this methodology is used to calculate power-optimal buffering schemes for various ITRS technology nodes for 5% delay penalty.
Book
Three-Dimensional Integrated Circuit Design
TL;DR: In this article, the first book on 3D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits.
References
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Proceedings ArticleDOI
Planning for performance
TL;DR: To achieve a non-iterative design flow, it is proposed that early synthesis stages should use "wireplanning" to distribute delays over the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays.
Journal ArticleDOI
The impact of technology scaling on ESD robustness and protection circuit design
A. Amerasekera,C. Duvvury +1 more
TL;DR: In this paper, the trend in ESD robustness as a function of technology scaling, for feature sizes down to 0.25 /spl mu/m, have been experimentally determined using single finger nMOS transistors and full ESD protection circuits.
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