Proceedings ArticleDOI
Power-aware test generation with guaranteed launch safety for at-speed scan testing
Xiaoqing Wen,K. Enokimoto,Kohei Miyase,Yuta Yamato,Michael A. Kochte,Seiji Kajihara,Patrick Girard,Mohammad Tehranipoor +7 more
- pp 166-171
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TLDR
This scheme is the first of its kind for achieving guaranteed launch safety with minimal impact on test quality and test costs, which is the ultimate goal of power-aware at-speed scan test generation.Abstract:
At-speed scan testing may suffer from severe yield loss due to the launch safety problem, where test responses are invalidated by excessive launch switching activity (LSA) caused by test stimulus launching in the at-speed test cycle. However, previous low-power test generation techniques can only reduce LSA to some extent but cannot guarantee launch safety. This paper proposes a novel & practical power-aware test generation flow, featuring guaranteed launch safety. The basic idea is to enhance ATPG with a unique two-phase (rescue & mask) scheme by targeting at the real cause of the launch safety problem, i.e., the excessive LSA in the neighboring areas (namely impact areas) around long paths sensitized by a test vector. The rescue phase is to reduce excessive LSA in impact areas in a focused manner, and the mask phase is to exclude from use in fault detection the uncertain test response at the endpoint of any long sensitized path that still has excessive LSA in its impact area even after the rescue phase is executed. This scheme is the first of its kind for achieving guaranteed launch safety with minimal impact on test quality and test costs, which is the ultimate goal of power-aware at-speed scan test generation.read more
Citations
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Journal ArticleDOI
Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing
TL;DR: Experimental results on ISCAS'89 and ITC'99 benchmark circuits show that an average of 75% of faults originally detected only by power-risky patterns can be detected by refining power-safe patterns and that most of the remaining faults can be detect by the low-power test generation process.
Proceedings ArticleDOI
A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation
TL;DR: This paper addresses the issue of vulnerability to IR-drop-induced yield loss in nano-scale designs with a novel per-cell dynamic IR- drop estimation method that achieves both high accuracy and high time-efficiency.
Proceedings ArticleDOI
On pinpoint capture power management in at-speed scan test generation
Xiaoqing Wen,Y. Nishida,Kohei Miyase,Seiji Kajihara,Patrick Girard,Mohammad Tehranipoor,Laung-Terng Wang +6 more
TL;DR: This paper proposes a novel scheme to manage capture power in a pinpoint manner for achieving guaranteed capture power safety, improved small-delay test capability, and minimal test cost impact in at-speed scan test generation.
Proceedings ArticleDOI
A novel scan segmentation design method for avoiding shift timing failure in scan testing
TL;DR: An optimal combination of scan segments is identified for simultaneous clocking so that the switching activity in the proximities of clock trees is reduced while maintaining the average power reduction effect on conventional scan segmentation.
Journal ArticleDOI
Low-Power Test Generation by Merging of Functional Broadside Test Cubes
TL;DR: Experimental results show that the procedure detects all or almost all the transition faults that are detectable by arbitrary (functional and nonfunctional) broadside tests in benchmark circuits.
References
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Survey of Test Vector Compression Techniques
TL;DR: This article summarizes and categories hardware-based test vector compression techniques for scan architectures, which fall broadly into three categories: code-based schemes use data compression codes to encode test cubes; linear-decompression- based schemes decompress the data using only linear operations; and broadcast-scan-based scheme rely on broadcasting the same values to multiple scan chains.
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Proceedings ArticleDOI
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TL;DR: A scheme for reducing power is presented and analysis results on an industrial design are provided and it is shown that circuit switching activity during scan shifting is high and results in high average and instantaneous power consumption.
Proceedings ArticleDOI
On low-capture-power test generation for scan testing
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