Proceedings ArticleDOI
Routability improvement using dynamic interconnect architecture
Jianmin Li,Chung-Kuan Cheng +1 more
- pp 61-67
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TLDR
This work presents a dynamic architecture for FPGA based computing systems with field programmable gate arrays and dynamic fieldprogrammable interconnect devices that overcomes FPGa pin limitations, but also greatly increases the routability of interconnect networks, resulting in higher overall performance of FGPA based systems.Abstract:
Field programmable gate arrays (FPGAs) have formed the basis for high performance and affordable computing systems. FPGA based logic simulators can emulate complex logic designs at clock speeds of several orders of magnitude faster than even accelerated software simulators, while FPGA based prototyping systems provide great flexibility in rapid prototyping and system verification. However, besides FPGA pin limitation, existing FPGA based systems also meet the problem of improving the routability of interconnect networks in the architecture design. We present a dynamic architecture for FPGA based computing systems with field programmable gate arrays and dynamic field programmable interconnect devices. Our architecture has advantages on FPGA gate utilization as well as on routability of interconnect networks. The central principle of this new architecture as based on the concept of efficiently exploiting the potential communication bandwidth of interconnect resources. By dynamically reconfiguring the interconnect networks, FPGA pins and interconnect resources are efficiently reused. In this way, this new architecture not only overcomes FPGA pin limitations, but also greatly increases the routability of interconnect networks, resulting in higher overall performance of FPGA based systems.read more
Citations
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Book
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Scott Hauck,André DeHon +1 more
TL;DR: This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology.
Journal ArticleDOI
The roles of FPGAs in reprogrammable systems
TL;DR: The promise and problems of reprogrammable systems are discussed, including an overview of the chip and system architectures of repprogrammable systems as well as the applications of these systems.
Patent
Dynamically programmable gate array with multiple contexts
André DeHon,Thomas F. Knight,Edward Tau,Michael Bolotski,Ian Eslick,Derrick Chen,Jeremy Brown +6 more
TL;DR: In this paper, a context signal generator is included that generates context signals indicating a change in an active one of the contexts, which can change as fast as every clock cycle of the programmable gate array.
Patent
DPGA-coupled microprocessors
TL;DR: In this paper, the authors describe a memory device having a plurality of memory banks and configurable logic units associated with the memory banks, which can be configured to the needs of the specific application.
Journal ArticleDOI
Logic emulation with virtual wires
TL;DR: Results, including in-circuit emulation of a SPARC microprocessor, indicate that virtual wires eliminate the need for expensive crossbar technology while increasing FPGA utilization beyond 45% andoretical analysis predicts thatvirtual wires emulation scales with FPN size and average routing distance, while traditional emulation does not.
References
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Building and using a highly parallel programmable logic array
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Proceedings ArticleDOI
Virtual wires: overcoming pin limitations in FPGA-based logic emulators
TL;DR: Results from compiling netlists indicate that virtual wires can increase FPGA gate utilization beyond 80 percent without a significant slowdown in emulation speed.
Journal ArticleDOI
GANGLION-a fast field-programmable gate array implementation of a connectionist classifier
C.E. Cox,W.E. Blanz +1 more
TL;DR: The authors take advantage of the reprogrammability of the devices to automatically generate new custom hardware for each application of the classifier, which is a totally digital connectionist classifier.
Journal ArticleDOI
An efficient logic emulation system
TL;DR: The Realizer, is a logic emulation system that automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented and its interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity.
Proceedings ArticleDOI
An efficient logic emulation system
TL;DR: The Realizer, a system which automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented, and the interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity.