Run-time generation of partial FPGA configurations

TLDR: The method is intended for use in adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance and is embodied in a code library that applications can use to create new bitstreams at run- time.

About: This article is published in Journal of Systems Architecture.The article was published on 2012-01-01 and is currently open access. It has received 3 citations till now. The article focuses on the topics: Netlist & Bitstream.

Figures

Fig. 5. Routing between stripes. (a) Placed components with indication of connections to be established; (b) detail of routing area (dashed box) showing one possible route connecting C to E.

Fig. 1. Platform used for the proof-of-concept implementation of run-time generation of bitstreams. PLB: 64-bit Processor Local Bus; OPB: 32-bit On-chip Peripheral Bus; ICAP: Internal Configuration Access Port.

Table 5 Running time improvement obtained by applying the route reuse heuristic after placement optimization with SA2D. Column ‘‘Impr.’’ shows the running time improvement achieved by the heuristic.

Table 1 Subset of FPGA routing resources that may be used for interconnecting components.

Fig. 2. Flow chart of bitstre

Table 2 Basic structural characteristics of all benchmark circuits used in the evaluation of the pro

Frequently asked questions

Q1. What are the contributions in "Run-time generation of partial fpga configurations" ?

This paper presents and evaluates a method of generating partial bitstreams at run-time for dynamic reconfiguration of sections of an FPGA. 

Q2. What is the standard synthesis flow for a Virtex-II Pro?

The standard synthesis flow produces a full bitstream for each component, which must be post-processed in order to extract the relevant partial bitstream and to add more information for use at run-time. 

Q3. What is the description of a router for just-in-time mapping of a?

A router for just-in-time mapping of a device-independent configuration description to a specific device architecture is described by [21]: it is able to produce good hardware circuits using 13 times less memory and executing 10 times faster than VPR [22] (running on a desktop computer). 

Q4. What is the role of RTR in the creation of new bitstreams?

The creation of the new bitstreams requires assigning positions of the reconfigurable area to components (placement), relocating and merging the individual component bitstreams, and interconnecting the components (routing) by modification of the merged bitstream. 

Q5. What is the role of the configuration memory controller?

The configuration memory controller is responsible for handling the actual transfer of the bitstreams to the configuration memory through the internal configuration access port (ICAP). 

Q6. How many CLBs are used to calculate a stripe density?

Since routes can cross stripes by going through the components or by using empty spaces, a stripe density value is calculated, which is given by the percentage of occupied CLBs. 

Q7. What is the first step of the bitstream?

At the beginning of the first step, the bitstream of the empty dynamic area is used to initialize the working array of configuration information. 

Q8. How would the physical interface adaptation be performed?

With the current system, the physical interface adaptation might be performed at run-time by adding appropriate ‘‘glue’’ components to the design. 

Q9. How long does it take to generate a bitstream?

The results for a set of 29 benchmarks (both synthetic and application-derived) show that time required for bitstream generation on a 300 MHz PowerPC embedded processor depends strongly on the complexity of the circuits, but is under 35 s for all benchmarks (average: 18 s). 

Q10. How much is the route reuse heuristic cost effective?

In general, the route reuse heuristic is very cost effective, because it provides an improvement in running time at a very low implementation cost. 

Q11. What is the procedure used to find a path between a source and a sink?

Procedure LinkPins (Alg. 3) is used to find a path from a source pin to one sink pin: it performs a breadth-first search for the shortest path between the source and sink terminals (line 4). 

Q12. What is the main task of the creation of a new partial bitstream?

In this work, the creation of a new partial bitstream involves three major tasks: placement, routing, and bitstream construction (Fig. 2). 

Q13. How many temperature decreases does the algorithm make?

The algorithm stops after a predefined number of temperature decreases (currently, 50), or if it fails to make any improvement for a fixed number of successive temperature decreases (currently, 10). 

Q14. What is the way to generate configurations?

The working implementation described here shows that runtime generation of configurations is a feasible technique for use on highly adaptive embedded systems, where it may be used to provide precisely-tailored hardware support for tasks whose computational needs exceed the computational power of the CPU. 

Q15. What is the significant improvement in routing time for benchmark H8?

The data of Table 3 show that the most significant improvement in routing time occurs for benchmark H8: with SA2D the routing time decreases 19.3%, for a global improvement of 15.9%. 

Q16. How much is the average length of the connections improved?

The average length of the connections is also systematically improved, in the best cases by more than one segment: M2 shows a reduction of 18.7% from 5.67 to 4.61 for the average length.