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Journal ArticleDOI

Sehwa: a software package for synthesis of pipelines from behavioral specifications

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TLDR
Sehwa can find the minimum-cost design, the highest performance design, and other designs between these two in the design space and executes within minutes, for problems of practical size, on a VAX 11/750.
Abstract
A set of techniques for the synthesis of pipelined data paths is described, and Sehwa, a program that performs such synthesis, is presented. The task includes the generation of data paths from a data-flow graph along with a clocking scheme that overlaps execution of multiple tasks. Some design examples are given. Sehwa can find the minimum-cost design, the highest performance design, and other designs between these two in the design space. Sehwa is written in Franz Lisp and executes within minutes, for problems of practical size, on a VAX 11/750. >

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Citations
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Proceedings ArticleDOI

PARAS: system-level concurrent partitioning and scheduling

TL;DR: Four algorithms (called PARAS) which can exploit this interaction by solving the scheduling and partitioning problems concurrently are presented and maximizes the overall performance of the final design and considers different chip configurations and communication structures.
Proceedings ArticleDOI

An iterative approach for hybria pipeline scheduling under throughput and resource constraints

TL;DR: A new approach for hybria pipeline scheduling problem is proposed, which can be applied to systems with non-pipelined, half pipelined or full pipeline components and is comparable with previous approaches.
Journal ArticleDOI

Synthesis of pipelined DSP accelerators with dynamic scheduling

TL;DR: A methodology is presented to synthesize high throughput DSP functions into accelerator processors containing a datapath of highly pipelined, bit-parallel hardware units.
Proceedings ArticleDOI

High-level DSP synthesis using the COMET design system

TL;DR: The authors address methodologies for high-level synthesis of dedicated digital signal processing (DSP) architectures using the cluster-oriented and minimum execution time (COMET) design system, capable of generating more efficient architectures using innovative scheduling and resource allocation algorithm.
Proceedings ArticleDOI

Design space exploration methodology for high-performance system-on-a-chip hardware cores

TL;DR: This paper is proposing an efficient design space exploration methodology based on a component point of view to system-on-a-chip (SOC) designs that reflects the current state-of-the-art behavioral synthesis process.
References
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Book ChapterDOI

First version of a data flow procedure language

TL;DR: The language is being used as a model for study of fundamental semantic constructs for programming, as a target language for evaluating trans-latability of programs expressed at the user-language level, and as a guide for research in advanced computer architecture.
Journal ArticleDOI

Data Flow Program Graphs

Davis, +1 more
- 01 Feb 1982 - 
TL;DR: Data flow languages form a subclass of the languages which are based primarily upon function application and graphical representations and their applications are the subject of this article.
Proceedings ArticleDOI

Improving the throughput of a pipeline by insertion of delays

TL;DR: A methodology is presented for modifying the collision characteristics with the insertion of delays so as to increase the utilization of segments and hence the throughput under appropriate scheduling.
Proceedings ArticleDOI

SEHWA: A Program for Synthesis of Pipelines

TL;DR: Sehwa is believed to be the first pipelined synthesis program published in the open literature and can find the minimum cost design, the highest performance design, and other designs between these two in the design space.
Proceedings ArticleDOI

The ADAM Advanced Design Automation System: Overview, Planner and Natural Language Interface

TL;DR: ADAM is described, an integrated Advanced Design AutoMation system, with focus on the knowledge-based synthesis subsystem, which includes a number of design activities and utilities, and a unified, multidimensional, hierarchical design representation.
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