Journal ArticleDOI
Significance-Aware Program Execution on Unreliable Hardware
Konstantinos Parasyris,Vassilis Vassiliadis,Christos D. Antonopoulos,Spyros Lalis,Nikolaos Bellas +4 more
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TLDR
A significance-centric programming model and runtime support that sets the supply voltage in a multicore CPU to sub-nominal values to reduce the energy footprint and provide mechanisms to control output quality is introduced.Abstract:
This article introduces a significance-centric programming model and runtime support that sets the supply voltage in a multicore CPU to sub-nominal values to reduce the energy footprint and provide mechanisms to control output quality. The developers specify the significance of application tasks respecting their contribution to the output quality and provide check and repair functions for handling faults. On a multicore system, we evaluate five benchmarks using an energy model that quantifies the energy reduction. When executing the least-significant tasks unreliably, our approach leads to 20% CPU energy reduction with respect to a reliable execution and has minimal quality degradation.read more
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Proceedings ArticleDOI
A Framework for Evaluating Software on Reduced Margins Hardware
Konstantinos Parasyris,Panos Koutsovasilis,Vassilis Vassiliadis,Christos D. Antonopoulos,Nikolaos Bellas,Spyros Lalis +5 more
TL;DR: Xtended Margins eXperiment Manager (XM^2) as mentioned in this paper supports both bare-metal and OS-controlled execution using an API to control the fault injection procedure and provides automatic management of experimental campaigns.
Journal ArticleDOI
SAIR: significance-aware approach to improve QoR of big data processing in case of budget constraint
TL;DR: The results indicate that SAIR improves QoR while meeting budget constraint for considered usages up to 15%, compared with the state of the art.
Proceedings ArticleDOI
HPAC: evaluating approximate computing techniques on HPC OpenMP applications
Konstantinos Parasyris,Giorgis Georgakoudis,Harshitha Menon,James Diffenderfer,Ignacio Laguna,Daniel Osei-Kuffuor,Markus Schordan +6 more
TL;DR: HPAC as mentioned in this paper is a framework with compiler and runtime support for code annotation and transformation, and accuracy vs. performance trade-off analysis of OpenMP HPC applications is performed.
Proceedings ArticleDOI
Exploring the potential of context-aware dynamic CPU undervolting
TL;DR: In this paper, a context-aware dynamic undervolting mechanism is proposed to decide and apply voltage levels according to the specific tolerance of each workload that executes on a multicore CPU at a particular time.
Journal ArticleDOI
ARETE: Accurate Error Assessment via Machine Learning-Guided Dynamic-Timing Analysis
Ioannis Tsiokanos,Styliani Tompazi,Giorgis Georgakoudis,Lev Mukhanov,Georgios Karakonstantis +4 more
TL;DR: ARETE as mentioned in this paper is a cross-layer fault-injection framework that combines dynamic-binary instrumentation with machine learning-guided dynamic-timing analysis to accelerate fault injection.
References
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Journal ArticleDOI
On sequential Monte Carlo sampling methods for Bayesian filtering
TL;DR: An overview of methods for sequential simulation from posterior distributions for discrete time dynamic models that are typically nonlinear and non-Gaussian, and how to incorporate local linearisation methods similar to those which have previously been employed in the deterministic filtering literature are shown.
Proceedings ArticleDOI
The PARSEC benchmark suite: characterization and architectural implications
TL;DR: This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs), and shows that the benchmark suite covers a wide spectrum of working sets, locality, data sharing, synchronization and off-chip traffic.
Proceedings ArticleDOI
Razor: a low-power pipeline based on circuit-level timing speculation
Daniel J. Ernst,Nam Sung Kim,Shidhartha Das,Sanjay Pant,Rajeev R. Rao,Toan Pham,Conrad H. Ziesler,David Blaauw,Todd Austin,Krisztian Flautner,Trevor Mudge +10 more
TL;DR: A solution by which the circuit can be operated even below the ‘critical’ voltage, so that no margins are required and thus more energy can be saved.
Journal ArticleDOI
EnerJ: approximate data types for safe and general low-power computation
TL;DR: EnerJ is developed, an extension to Java that adds approximate data types and a hardware architecture that offers explicit approximate storage and computation and allows a programmer to control explicitly how information flows from approximate data to precise data.
Proceedings ArticleDOI
Managing performance vs. accuracy trade-offs with loop perforation
TL;DR: The results indicate that, for a range of applications, this approach typically delivers performance increases of over a factor of two (and up to a factors of seven) while changing the result that the application produces by less than 10%.