Razor: a low-power pipeline based on circuit-level timing speculation
Daniel J. Ernst,Nam Sung Kim,Shidhartha Das,Sanjay Pant,Rajeev R. Rao,Toan Pham,Conrad H. Ziesler,David Blaauw,Todd Austin,Krisztian Flautner,Trevor Mudge +10 more
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TLDR
A solution by which the circuit can be operated even below the ‘critical’ voltage, so that no margins are required and thus more energy can be saved.Abstract:
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for power-aware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essential to scale the supply voltage as low as possible while ensuring correct operation of the processor. The critical voltage is chosen such that under a worst-case scenario of process and environmental variations, the processor always operates correctly. However, this approach leads to a very conservative supply voltage since such a worst-case combination of different variabilities is very rare. In this paper, we propose a new approach to DVS, called Razor, based on dynamic detection and correction of circuit timing errors. The key idea of Razor is to tune the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time-borrowing delayed clock. A metastability-tolerant comparator then validates latch values sampled with the fast clock. In the event of timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. A prototype Razor pipeline was designed in a 0.18 /spl mu/m technology and was analyzed. Razor energy overhead during normal operation is limited to 3.1%. Analyses of a full-custom multiplier and a SPICE-level Kogge-Stone adder model reveal that substantial energy savings are possible for these devices (up to 64.2%) with little impact on performance due to error recovery (less than 3%).read more
Citations
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Designing reliable systems from unreliable components: the challenges of transistor variability and degradation
TL;DR: This article discusses effects of variability in transistor performance and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.
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EnerJ: approximate data types for safe and general low-power computation
TL;DR: EnerJ is developed, an extension to Java that adds approximate data types and a hardware architecture that offers explicit approximate storage and computation and allows a programmer to control explicitly how information flows from approximate data to precise data.
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RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance
Shidhartha Das,Carlos Tokunaga,Sanjay Pant,Wei-Hsiang Ma,S. Kalaiselvan,Kevin Lai,David Michael Bull,David Blaauw +7 more
TL;DR: This paper presents a design (RazorII) which implements a flip-flop with in situ detection and architectural correction of variation-induced delay errors and demonstrates SER tolerance on the RazorII processor through radiation experiments.
Proceedings ArticleDOI
Circuit Failure Prediction and Its Application to Transistor Aging
TL;DR: Simulation results using 90nm and 65nm technologies demonstrate that a new sensor design integrated inside a flip-flop enables efficient circuit failure prediction at a low cost and can significantly improve system performance by enabling close to best- case design instead of traditional worst-case design.
Proceedings ArticleDOI
Flikker: saving DRAM refresh-power through critical data partitioning
TL;DR: Flikker exposes and leverages an interesting trade-off between energy consumption and hardware correctness, and shows that many applications are naturally tolerant to errors in the non-critical data, and in the vast majority of cases, the errors have little or no impact on the application's final outcome.
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