Proceedings ArticleDOI
Statistical logic cell delay analysis using a current-based model
Hanif Fatemi,Shahin Nazarian,Massoud Pedram +2 more
- pp 253-256
TLDR
A new current-based cell delay model is utilized, which can accurately compute the output waveform for input waveforms of arbitrary shapes subjected to noise, and the cell parasitic capacitances are pre-characterized by lookup tables to improve the accuracy.Abstract:
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can accurately compute the output waveform for input waveforms of arbitrary shapes subjected to noise. The cell parasitic capacitances are pre-characterized by lookup tables to improve the accuracy. To capture the effect of process parameter variations on the cell behavior, the output voltage waveform of logic cells is modeled by a stochastic Markovian process in which the voltage value probability distribution at each time instance is computed from that of the previous time instance. Next the probability distribution of a % V/sub dd/ crossing time, i.e., the hitting time of the output voltage stochastic process is computed. Experimental results demonstrate the high accuracy of our cell delay model compared to Monte-Carlo-based SPICE simulations.read more
Citations
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Proceedings ArticleDOI
Statistical waveform and current source based standard cell models for accurate timing analysis
Amit Goel,Sarma Vrudhula +1 more
TL;DR: A statistical current source based gate model is developed that can accurately generate the signal waveform at any process corner for accurate timing analysis and shows very good correlation with SPICE.
Proceedings ArticleDOI
A current source model for CMOS logic cells considering multiple input switching and stack effect
TL;DR: A current source model (CSM) of a CMOS logic cell, which captures simultaneous switching of multiple inputs while accounting for the effect of internal node voltages of the logic cell is presented.
Proceedings ArticleDOI
A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms
TL;DR: An accurate model is presented to calculate the short circuit energy dissipation of logic cells using a current-based logic cell model, which constructs the output voltage waveform for a given noisy input waveform.
Patent
Methods and apparatus for waveform based variational static timing analysis
TL;DR: In this paper, a waveform based variational static timing analysis is presented, where a circuit is divided into its linear circuit parts and non-linear circuit parts, and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices.
Journal ArticleDOI
Accurate Timing and Noise Analysis of Combinational and Sequential Logic Cells Using Current Source Modeling
TL;DR: A highly accurate CSM for combinational logic cells is presented, followed by models for common sequential cells, including latches and master slave flip-flops, which can be used for accurate noise and delay analysis in CMOS VLSI circuits.
References
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Proceedings ArticleDOI
First-order incremental block-based statistical timing analysis
TL;DR: In this article, a canonical first order delay model is proposed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form and the sensitivities of all timing quantities to each of the sources of variation are available.
Proceedings ArticleDOI
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
TL;DR: An efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay while incorporating the effects of spatial correlations of intra-die parametervariations, using a method based on principal component analysis.
Proceedings ArticleDOI
Modeling and analysis of manufacturing variations
TL;DR: In this article, the authors examine the sources and trends of process variability, the new challenges associated with the increase in within-die variability analysis, and propose a modeling and simulation methodology to deal with this variability.
Journal ArticleDOI
First-Order Incremental Block-Based Statistical Timing Analysis
Chandu Visweswariah,Kaushik Ravindran,Kerim Kalafala,Steven G. Walker,Sambasivan Narayan,D.K. Beece,Jeffrey S. Piaget,Natesan Venkateswaran,Jeffrey G. Hemmett +8 more
TL;DR: A canonical first-order delay model that takes into account both correlated and independent randomness is proposed, and the first incremental statistical timer in the literature is reported, suitable for use in the inner loop of physical synthesis or other optimization programs.
Proceedings ArticleDOI
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
TL;DR: The authors' technique improves accuracy in predicting circuit timing characteristics and retains such benefits of parameterized block-based statistical STA as an incremental mode of operation, computation of criticality probabilities and sensitivities to process parameter variations.