Study on the effects of wafer thinning and dicing on chip strength

TLDR: In this paper, the authors identified the weak regions, in terms of mechanical strength, in chips in a semiconductor wafer using the three-point bending test, which was observed in two sectors approximately 45/spl deg/m wide, axisymmetric to the wafer center.

Abstract: Die cracking is an annoying problem in the packaging industry. In this paper, we identified the weak regions, in terms of mechanical strength, in chips in a semiconductor wafer using the three-point bending test. The weak regions were observed in two sectors approximately 45/spl deg/ wide, axisymmetric to the wafer center. The strength of the chips within these weak regions was about 30%-35% lower than the average chip strength of the whole wafer. The existence of these weak regions was related to spiral grinding marks, which, in turn, were formed by backside mechanical grinding. The probability distributions of the chip strength and the chip fragmentary pattern confirmed this relationship. When wafers were mechanically ground until they were 50-/spl mu/m thick, chip warpage was found to be oriented to the direction of the grinding marks. Meanwhile, by slowing the mechanical grinding speed by 50%, we were able to increase the average chip strength by 56%. Either plasma etching or polishing after mechanical grinding eliminated the weak regions, and the optimal amount of mechanical grinding and the polishing depths were observed, beyond which the chip strength would not increase. On the other hand, a preprocess for blunting a new saw blade for chip dicing was found to be essential as the chip strength increased five-fold, whereas increasing the dicing speed or using dual saw instead of a single saw had only small effects on the chip strength degradation.