Journal ArticleDOI
Switched-capacitor delay circuit that is insensitive to capacitor mismatch and stray capacitance
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TLDR
In this paper, a switched-capacitor delay circuit which uses only a single amplifier and is insensitive to capacitor mismatch and stray capacitance is proposed, which permits the use of very small-valued capacitors so that the chip area can be reduced by device scaling as the feature sizes are reduced.Abstract:
A new switched-capacitor delay circuit which uses only a single amplifier and is insensitive to capacitor mismatch and stray capacitance is proposed. The insensitivity to capacitor mismatch permits the use of very small-valued capacitors so that the chip area can be reduced by device scaling as the feature sizes are reduced due to improvements in technology. Tapped analogue delay lines using such delay elements would be ideal for realising programmable and adaptive filters and equalisers in analogue LSI.read more
Citations
More filters
Journal ArticleDOI
A CMOS analog continuous-time delay line with adaptive delay-time control
K. Bult,H. Wallinga +1 more
TL;DR: A CMOS analog continuous-time delay line composed of cascaded first-order current-domain all-pass sections is discussed, based on the square-law characteristic of an MOS transistor in saturation.
Journal ArticleDOI
A 700-MHz switched-capacitor analog waveform sampling circuit
Gunther Haller,Bruce A. Wooley +1 more
TL;DR: In this article, an experimental two-channel memory with 32 sampling cells in each channel has been integrated in a 2/spl mu/m CMOS technology with poly-to-poly capacitors.
Journal ArticleDOI
Effects of coefficient inaccuracy in switched-capacitor transversal filters
TL;DR: In this paper, an exact probability distribution function is derived for the error in the frequency response, which can be characterized by a Rayleigh distribution, which is then used to derive an upper bound for the expected stopband attenuation.
Journal ArticleDOI
Adaptive switched-capacitor filters based on the LMS algorithm
U. Menzi,George S. Moschytz +1 more
TL;DR: In this article, an adaptive FIR filter based on the LMS algorithm using SC circuits is described, which consists of a delay element, a summing circuit, an integrator, and a multiplier.
Patent
Differential switched capacitor filtering
TL;DR: In this article, a differential switched capacitor filter section which comprises a differential amplifier (OTA), a first set of switched capacitors (C11, C12, C21, C22) coupled between an inverting output and a non-inverting input of the differential amplifier is presented.
References
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Journal ArticleDOI
MOS switched-capacitor analog sampled-data direct-form recursive filters
Ian A. Young,David A. Hodges +1 more
TL;DR: The direct form switched-capacitor offers some useful advantages in comparison to the switched-Capacitor integrator approach, including the rejection of MOS amplifier noise and power supply noise below one-half the sampling rate, less silicon area especially when implementing high Q poles, and potential for multiplexing two or more filters.
Journal ArticleDOI
Integrated tapped MOS analogue delay line using switched capacitor technique
TL;DR: In this paper, a tapped MOS analogue delay line based on the switched capacitor technique for realisation of low-power analogue LSIs is fabricated using a VLSI process, with excellent characteristics such as large signal handling capability, low total harmonic distortion of −85 dB for 3V(p-p) input and fast operation speed with negligible charge transfer loss.
Journal ArticleDOI
Charge-coupled device (CCD) adaptive discrete analog signal processing
TL;DR: A CCD adaptive signal processor is described which uses a so-called `clipped-data' least mean square (LMS) error algorithm to optimize the selection of tap weights in a CCD filter.
Journal ArticleDOI
Stray-free switched-capacitor unit-delay circuit
TL;DR: In this article, a two-phase stray-insensitive switched-capacitor unit-delay circuit using only one operational amplifier is presented, and the implementation of sampled analogue filters based on digital-filter architectures using this circuit as a building block is demonstrated.
Journal ArticleDOI
A monolithic adaptive filter
TL;DR: In this article, a monolithic adaptive filter is proposed using analog sampled-data MOS and CCD techniques. The filter implements a full Widrow least mean-squares algorithm over 65 data points and operates at sample rates up to 100 kHz.