Patent
Technique to mitigate short channel effects with vertical gate transistor with different gate materials
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TLDR
In this paper, a process of forming a transistor with three vertical gate electrodes and the resulting transistor maintaining an acceptable aspect ratio as MOSFET structures are scaled down to sub-micron sizes is described.Abstract:
This invention relates to a process of forming a transistor with three vertical gate electrodes and the resulting transistor. By forming such a transistor it is possible to maintain an acceptable aspect ratio as MOSFET structures are scaled down to sub-micron sizes. The transistor gate electrodes can be formed of different materials so that the workfunctions of the three electrodes can be tailored. The three electrodes are positioned over a single channel and operate as a single gate having outer and inner gate regions.read more
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References
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Journal ArticleDOI
Dual-material gate (DMG) field effect transistor
TL;DR: In this paper, the dual material gate (DMG) FET was proposed and demonstrated, where the gate consists of two laterally contacting materials with different work functions, such that the threshold voltage near the source is more positive than that near the drain, resulting in a more rapid acceleration of charge carriers in the channel.
Patent
Multilayer dielectric stack and method
Yanjun Ma,Yoshi Ono +1 more
TL;DR: In this paper, a multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material, which reduces the effects of crystalline structures within individual layers.
Patent
MOS transistor with assisted-gates and ultra-shallow “Psuedo” source and drain extensions for ultra-large-scale integration
TL;DR: In this paper, the composite gate structure is comprised of a main gate and two assisted-gate electrodes disposed adjacent to and on opposite sides of the main gate electrode via an oxide layer.
Patent
Integrated processing and L2 DRAM cache
TL;DR: In this article, an integrated processor and level two (L2) dynamic random access memory (DRAM) are fabricated on a single chip, and the L2 DRAM cache is placed on the same chip as the processor to reduce the time needed for two chip-to-chip crossings.
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Nonvolatile memory cell, operating method of the same and nonvolatile memory array
Seiki O. Ogura,Yutaka Hayashi +1 more
TL;DR: In this paper, a nonvolatile memory cell and/or array and a method of operating the same high integrated density NVRAM cell enabling high integration density, low voltage programming and high speed programming is presented.