Technology mapping and architecture evalution for k/m-macrocell-based FPGAs
Jason Cong,Hui Huang,Xin Yuan +2 more
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TLDR
A very efficient technology mapping algorithm, k_m_flow, is developed for a novel field-programmable gate array (FPGA) architecture that is based on k-input single-output programmable logic array- (PLA-) like cells, or, k/m-macrocells and can outperform 4-LUT-based FPGAs on this set of benchmarks.Abstract:
In this article, we study the technology mapping problem for a novel field-programmable gate array (FPGA) architecture that is based on k-input single-output programmable logic array- (PLA-) like cells, or, k/m-macrocells. Each cell in this architecture can implement a single output function of up to k inputs and up to m product terms. We develop a very efficient technology mapping algorithm, klmlflow, for this new type of architecture. The experimental results show that our algorithm can achieve depth-optimality on almost all the testcases in a set of 16 Microelectronics Center of North Carolina (MCNC) benchmarks. Furthermore it is shown that on this set of benchmarks, with only a relatively small number of product terms (m ≤ k p 3), the k/m-macrocell-based FPGAs can achieve the same or similar mapping depth compared with the traditional k-input single-output lookup table- (k-LUT-) based FPGAs. We also investigate the total area and delay of k/m-macrocell-based FPGAs and compare them with those of the commonly used 4-LUT-based FPGAs. The experimental results show that k/m-macrocell-based FPGAs can outperform 4-LUT-based FPGAs in terms of both delay and area after placement and routing by VPR on this set of benchmarks.read more
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References
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Logic Minimization Algorithms for VLSI Synthesis
TL;DR: The ESPRESSO-IIAPL as discussed by the authors is an extension of the ESPRSO-IIC with the purpose of improving the efficiency of Tautology and reducing the number of blocks and covers.
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Architecture and CAD for Deep-Submicron FPGAS
TL;DR: From the Publisher: Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools, with particular emphasis on issues that are important for FPG as implemented in deep-submicron processes.
Journal ArticleDOI
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
Jason Cong,Yuzheng Ding +1 more
TL;DR: A theoretical breakthrough is presented which shows that the LUT-based FPGA technology mapping problem for depth minimization can be solved optimally in polynomial time.
Journal ArticleDOI
Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency
TL;DR: It was observed that the area efficiency of a logic block depends not only on its functionality but also on the average number of pins connected per logic block.
Proceedings ArticleDOI
Chortle-crf: Fast technology mapping for lookup table-based FPGAs
TL;DR: A new technology mapping algorithm for lookup tablebased Field Programmable Gate Arrays (FPGA) is presented, the major innovation is a method for choosing gate-level decompositions based on bin packing that is up to 28 times faster than a previous exhaustive approach.
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