760 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 5, MAY 2010
Test-Pattern Selection for Screening Small-Delay
Defects in Very-Deep Submicrometer
Integrated Circuits
Mahmut Yilmaz, Member, IEEE, Krishnendu Chakrabarty, Fellow, IEEE, and
Mohammad Tehranipoor,
Senior Member, IEEE
Abstract—Timing-related defects are major contributors to
test escapes and in-field reliability problems for very-deep sub-
micrometer integrated circuits. Small delay variations induced
by crosstalk, process variations, power-supply noise, as well as
resistive opens and shorts can potentially cause timing failures
in a design, thereby leading to quality and reliability concerns.
We present a test-grading technique that uses the method of
output deviations for screening small-delay defects (SDDs). A new
gate-delay defect probability measure is defined to model delay
variations for nanometer technologies. The proposed technique
intelligently selects the best set of patterns for SDD detection
from an n-detect pattern set generated using timing-unaware
automatic test-pattern generation (ATPG). It offers significantly
lower computational complexity and excites a larger number
of long paths compared to a current generation commercial
timing-aware ATPG tool. Our results also show that, for the
same pattern count, the selected patterns provide more effective
coverage ramp-up than timing-aware ATPG and a recent pattern-
selection method for random SDDs potentially caused by resistive
shorts, resistive opens, and process variations.
Index Terms—Delay test, output deviations, process variations,
small-delay defects, test-pattern grading.
I. Introduction
V
ERY DEEP submicrometer (VDSM) process technolo-
gies are leading to increasing densities and higher clock
frequencies for integrated circuits (ICs). However, VDSM
technologies are especially susceptible to process variations,
crosstalk noise, power-supply noise, and defects such as resis-
tive shorts and opens, which induce small delay variations in
the circuit components. Such delay variations are referred to
as small-delay defects (SDDs) in the literature [1], [2].
Manuscript received October 17, 2008; revised February 10, 2009, Sep-
tember 15, 2009, and December 11, 2009. Current version published
April 21, 2010. The work of M. Yilmaz and K. Chakrabarty was sup-
ported in part by the Semiconductor Research Corporation (SRC), un-
der contract 1588, and by the National Science Foundation (NSF), un-
der Grant ECCS-0823835. The work of M. Tehranipoor was supported
in part by SRC, under contracts 1455 and 1587, and by NSF, under
Grant ECCS-0823992. This paper was recommended by Associate Editor,
R. D. (Shawn) Blanton.
M. Yilmaz is with the Design-for-Test Team, Advanced Micro Devices, Inc.,
Sunnyvale, CA 94085 USA (e-mail: mahmut.yilmaz@amd.com).
K. Chakrabarty is with the Department of Electrical and Computer Engineer-
ing, Duke University, Durham, NC 27708 USA (e-mail: krish@ee.duke.edu).
M. Tehranipoor is with the Department of Electrical and Computer
Engineering, University of Connecticut, Storrs, CT 06269 USA (e-mail:
tehrani@engr.uconn.edu).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCAD.2010.2043591
Although the delay introduced by each SDD is small, the
overall impact can be significant if the target path is critical,
has low slack, or includes many SDDs. The overall delay of the
path may become longer than the clock period, causing circuit
failure or temporarily incorrect results. As a result, the detec-
tion of SDDs typically requires fault excitation through least-
slack paths. The longest paths in the circuit, except false paths
and multi-cycle paths, are referred to as the least-slack paths.
The transition delay-fault (TDF) [3] model attempts to
propagate the lumped delay defect of a gate by logical
transitions to the observation points or state elements. The
effectiveness of the TDF model for SDDs has often been
questioned [1], [4] due to its tendency to excite transition
delay-faults through short paths [1].
Due to the growing interest in SDDs, the first commercial
timing-aware automatic test-pattern generation (ATPG) tools
were introduced recently, e.g., new versions of Mentor Graph-
ics FastScan, Cadence Encounter Test, and Synopsys TetraMax
[5]–[7]. These tools attempt to make ATPG patterns more
effective for SDDs by exercising longer paths or applying pat-
terns at higher-than-rated clock frequencies. However, only a
limited amount of timing information is supplied to these tools,
either via standard delay format (SDF) files (for FastScan and
Encounter Test) or through a static timing analysis (STA) tool
(for TetraMax). As a result, none of these tools can be easily
extended to take into account process variations, crosstalk,
power-supply noise, or similar SDD-inducing effects on path
delays. These tools simply rely on the assumption that the
longest paths (determined using STA or SDF data) in a design
are more prone to failure due to SDDs. Moreover, the test
generation time increases considerably when these tools are
run in timing-aware mode. Fig. 1 shows a comparison of the
run times of two current generation ATPG tools from the same
EDA company: 1) timing-unaware ATPG, i.e., a traditional
transition-delay-fault pattern generator; and 2) timing-aware
ATPG that takes timing information into account. The results
are shown for some of the International Workshop on Logic
and Synthesis (IWLS) 2005 benchmarks [8] and the absolute
run times are shown in [9]. It can be seen from Fig. 1 that,
when the benchmark is large, the timing-aware ATPG takes
significantly more central processing unit (CPU) time, e.g.,
as much as 209 times more for the “netcard” benchmark. The
CPU times in Fig. 1 reflect distributed ATPG results using
0278-0070/$26.00
c
2010 IEEE
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YILMAZ et al.: TEST-PATTERN SELECTION FOR SCREENING SMALL-DELAY DEFECTS IN VERY-DEEP 761
Fig. 1. Comparison of ATPG run times (CPU time): timing-aware ATPG
relative to timing-unaware ATPG for IWLS’2005 benchmarks.
eight processors, and the numbers are normalized such that
the run-time of timing-unaware ATPG is taken to be one unit.
The complexity of today’s ICs and shrinking process tech-
nologies are also leading to prohibitively high test-data vol-
umes. For example, the volume for TDFs is two to five times
higher than that for stuck-at faults [10], and it has been
demonstrated recently that test patterns for such sequence and
timing-dependent faults are more important for newer tech-
nologies [11]. The 2007 International Technology Roadmap
for Semiconductors predicted that the test data volume for
integrated circuits will be as much as 38 times larger and the
test application time will be about 17 times longer in 2015
than it was in 2007 [12]. Therefore, efficient pattern-selection
methods are required to reduce the total pattern count while
effectively targeting SDDs.
This paper presents the output deviation measure [13],
[14] as a surrogate coverage metric for SDDs and a test-
pattern grading method to select the best patterns for SDD
detection from a large repository test set. A flexible, but
general, probabilistic fault model is used to target defects. The
proposed method can be used with traditional, timing-unaware
ATPG tools to generate a high-quality and compact delay-fault
pattern set. It can also be used to select the most effective
patterns from large timing-aware test sets. Experimental results
show that the proposed method can effectively select the
highest quality patterns from large test sets that cannot be
used in their entirety for production test environments with
tight pattern-count limits. It also considers process-variability-
induced delay variations, unlike most previous methods. The
proposed approach requires significantly less CPU time than
a commercial timing-aware ATPG tool under pattern-count
limits. For various metrics, namely coverage of long paths,
detection of injected defects, and coverage ramp-up, it is
shown to outperform a commercial timing-aware ATPG tool.
We also compare the proposed method with the approach
proposed by Lee et al. [15], in which path-length calculations
are approximated for better run-time, and we highlight better
long-path coverage, lower run times, and faster coverage ramp-
up for injected faults.
In the remainder of this paper, Section II presents related
prior work in the area of SDDs. In Section III, we describe the
probabilistic fault model and the output deviations metric. Sec-
tion III-D presents the proposed pattern-selection procedures.
In Section IV, we evaluate the proposed method for benchmark
circuits and n-detection TDF test sets. We also conduct simu-
lated defect-injection experiments to evaluate the effectiveness
of the selected patterns for detecting small delays caused by
resistive shorts and opens. Section V concludes this paper.
II. Related Prior Work
SDDs were first alluded to in [16]. In recent years, high-
quality delay-fault pattern generation for SDDs has received
increasing attention. Most of the work is aimed at finding the
longest paths in a circuit. Gupta et al. [17] have proposed
the as late as possible transition fault model, which attempts
to launch one or more transitions at the fault site as late
as possible, i.e., through the least-slack path using robust
tests. This method suffers from the need for a complex,
time-consuming search procedure and robust test-generation
constraints. Qui et al. [18] attempt to find the k-longest paths
(referred to as KLPG) through the inputs and output of each
gate for slow-to-rise and slow-to-fall faults. Similar to [17], a
considerable amount of pre-processing is needed to search for
long paths. Furthermore, a long path through a gate may be a
short path in the circuit; thus, not all the paths determined by
the method are least-slack paths. Ahmed et al. [1] use STA
tools to find long, intermediate (IP), and short paths (SP) to
each observation point. Using a timing-unaware ATPG tool,
15-detect transition test patterns are generated. During pattern
generation, constraints are applied on IP and SP observation
points to mask them. In this way, the ATPG tool is forced
to generate patterns for LPs. In the post-processing phase,
a pattern-selection algorithm is used to pick patterns that
activate the largest number of end-points. Similar to previous
methods, a time-consuming search procedure is needed for
determining long paths and for path classification. A functional
delay-fault test generation method is proposed in [19]. This
method generates sequences of instructions for testing delay
faults. However, it requires a fault-free unit that can run the
instructions for the test program. Similar to earlier methods,
this scheme also involves a lengthy preprocessing step. In [20],
delay defects within slack intervals are detected by using a
clock frequency higher than the rated clock frequency. This
method uses a good neighboring die to test the surrounding
dies. The responses of the good die and the other dies are
compared with each other to find delay defects. A new
fault model, called the “transition path delay fault model,”
is described in [21]. This fault model relaxes the robustness
constraint required by the path-delay fault model, and aims to
excite paths that are missed by the path-delay fault model. [22]
presents a method to accurately determine the fault coverage
of path-delay tests by analyzing path reconvergences. This
method is applicable to the bounded gate-delay model.
As a result of increasing industry concern regarding SDDs,
companies such as Mentor Graphics, Cadence, and Synopsys
have recently released timing-aware ATPG tools [2], [5]–[7].
Lin et al. [2] use SDF files to guide ATPG to generate
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762 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 5, MAY 2010
transition test through long paths. In a pre-processing step,
the proposed method evaluates the delay for “activation” and
“propagation” paths for each gate to find longest paths. Test
generation is guided by the results of this pre-processing step.
Although approximation methods are used to decrease the
overhead associated with delay and path-length calculations,
this method still takes considerably more time compared to
timing-unaware ATPG tool. Kapur et al. [7] use STA tool-
generated pin slack information to guide timing-aware ATPG.
Although the pre-processing step is skipped by pushing the
slack data calculation to the STA tool, pattern generation takes
considerably more time than timing-unaware ATPG.
Statistical static timing analysis (SSTA) can generate
variability-aware delay data. It is demonstrated in recent papers
[23], [24] that traditional SSTA does not find sensitized paths
based on input vectors using statistical data. Furthermore, a
complete SSTA flow takes considerable computation time [25],
[26]. However, simplified-SSTA-based approaches can be used
for pattern selection, as shown in [27], [28]. In [27], authors
propose an SSTA-based test pattern quality metric for the
detection of SDDs. The computation of the metric requires
multiple dynamic timing analysis runs for each test pattern
using randomly sampled delay data from Gaussian pin-to-pin
delay distributions. The proposed metric is also used for pat-
tern selection. In [28], the authors focus on timing-hazards and
propose a timing-hazard-aware SSTA-based pattern selection
technique. A qualitative comparison of both of these SSTA-
based techniques to our method can be found in Section IV-D.
The “number of activated long paths” is a useful metric
for evaluating the quality of delay-fault pattern quality, but
a more computationally tractable method is clearly needed.
An alternative evaluation method, referred to as the statistical
delay quality model (SDQM), has been proposed by Sato et al.
[29]. This pattern-grading metric is based on a delay-defect
distribution function, which requires delay-defect statistics for
fabricated ICs. The method assigns a statistical delay quality
level to each test set to evaluate its quality. A drawback of
this metric is the need for delay-defect distributions for real
chips. This data is not available before volume production and
it is difficult and very expensive to obtain it during production
test. Another shortcoming of SDQM and similar metrics is
that they require knowledge of the longest sensitizable paths,
which is not accurately known before production test.
III. Probabilistic Delay-Fault Model and Output
Deviations for SDDs
In this section, we first introduce the concept of gate-
delay defect probabilities (DDPs) (Section III-A) and signal-
transition probabilities (Section III-B). These probabilities
extend the notion of confidence levels, defined in [13] for a
single pattern, to pattern-pairs. Next, we show how to use these
probability values to propagate the effects of a test pattern
to the test observation points (scan flip-flops/primary outputs)
(Section III-B). We describe the algorithm used for signal-
probability propagation (Section III-C). Finally, we describe
how test patterns can be ranked and selected from a large
repository (Section III-D).
TABLE I
Example DDPM for a 2-Input OR Gate
Initial Input State
OR prob 00
01 10
11
Inputs
IN0 0.5 0
0.5
0.1
IN1 0.2
0.2 0
A. Gate-Delay Defect Probabilities
DDPs are assigned to each gate in a design. DDPs for a gate
are provided in the form of a matrix called the delay defect
probability matrix (DDPM). The DDPM for a 2-input OR gate
is shown in Table I. The rows in the matrix correspond to each
input port of the gate and the columns correspond to the initial
input state during a transition.
Assume that the inputs are shown in the order of IN0,
IN1. If there is an input transition from “10” to “00,” the
corresponding DDPM column is “10.” Since the transition is
caused by IN0, the corresponding DDPM row is IN0.Asa
result, the delay-defect probability (DDP) value corresponding
to this event is 0.5. 0.5, showing the probability that corre-
sponding output transition is delayed beyond a threshold.
For initial state “11,” both inputs should switch simulta-
neously to have an output transition. Corresponding DDPM
entries are merged due to this requirement. The entries in
Table I have been chosen arbitrarily for the sake of illustration.
The real DDPM entries are much smaller than the ones shown
in this example.
For an N-input gate, the DDPM consists of N · 2
N
entries,
each holding one probability value. If the gate has more than
one output, each output of the gate has a different DDPM. Note
that the DDP is 0 if the corresponding event cannot provide
an output transition. Consider DDPM(2, 3) in Table I. When
the initial input state is “10,” no change in IN1 can cause
an output transition, because the OR gate output is already at
high state, and even if IN1 switches to high (1), this will not
cause an output transition.
We next discuss how a DDPM is generated. Each entry in
DDPM indicates the probability that the delay of a gate is
more than a predetermined value, i.e., the critical delay value
(T
CRT
). Given the probability density function (PDF) of a delay
distribution, the DDP is calculated as
DDP = Prob(x>T
CRT
)=
∞
T
CRT
PDF (x) dx. (1)
For instance, if we assume a Gaussian delay distribution
for all gates (with mean µ) and set the critical delay value to
µ + X, each DDP entry can be calculated by replacing T
CRT
with µ + X and using a Gaussian PDF. Note that the delay for
each input-to-output transition may have a different mean (µ)
and standard deviation (σ). The selection of X is described in
Section IV-A.
The delay distribution can be obtained in different ways:
1) using the delay information provided by an SSTA-generated
SDF file; 2) using slow, nominal, and fast process corner
transistor models; and 3) simulating process variations. In
the third method, which is employed in this paper, transistor
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YILMAZ et al.: TEST-PATTERN SELECTION FOR SCREENING SMALL-DELAY DEFECTS IN VERY-DEEP 763
parameters affecting the process variation and the limits of the
process variation (3σ) are first determined. Monte Carlo (MC)
simulations are next run for each library gate under different
capacitive loading and input slew rate conditions. Once the
distributions are found for the library gates, depending on
the layout, the delay distributions for each individual gate
can be updated. Once the distributions are obtained, T
CRT
can be appropriately set to compute the DDPM entries.
The effects of crosstalk can be simulated separately and the
delay distributions of individual gates/wires can be updated
accordingly.
The generation of the DDPMs is not the main focus of this
paper. We consider DDPMs to be analogous to timing libraries.
Our goal is not to develop the most effective techniques for
constructing DDPMs; rather, we are using such statistical data
to compute deviations and use them for pattern grading and
pattern selection. In a standard industrial flow, statistical timing
data can be developed by specialized timing groups, so the
generation of DDPMs is a pre-processing step and an input to
the ATPG-focused test-automation flow.
We have also seen that small changes in the DDPM entries
have negligible impact on the pattern-selection results. We
attribute this finding to the fact that any DDPM changes affect
multiple paths in the circuits, so their impact is amortized
over the circuit and the test set. The absolute values of the
output deviations are less important than the relative values
for different test patterns. Detailed results are presented in
Section IV-G and in [9].
B. Propagation of Signal-Transition Probabilities
Since pattern pairs are required to detect TDFs, there can
be a transition on each net of the circuit for every pattern pair.
If we assume that there are only two possible logic values
for a net, i.e., LOW (L) and HIGH (H), the possible signal-
transitions are L → L, L → H, H → L, and H → H. Each
of these transitions has a corresponding probability, denoted
by P
L→L
, P
L→H
, P
H→L
, and P
H→H
, respectively, in a vector
form (< ... >): <P
L→L
,P
L→H
,P
H→L
,P
H→H
>. We refer
to this vector as the signal-transition probability (STP) vector.
Note that L → L or H → H implies that the net keeps its
value, i.e., no transition occurs.
The nets that are directly connected to the test-application
points are called initialization nets (INs). These nets have
one of the STPs, corresponding to the applied transition test
pattern, equal to 1. All the other STPs for INs are set to 0.
When signals are propagated through several levels of gates,
the STPs can be computed using the DDPM of the gates.
Note that interconnects can also have DDPMs to account for
crosstalk. In this paper, due to the lack of layout information,
we only focus on variations’ impact on gate delay. The overall
deviation-based framework is, however, general and it can
easily accommodate interconnect delay variations if layout
information is available, as has been reported in [30].
Definition 1: Let P
E
be the probability that a net has the
expected signal-transition. The deviation on that net is defined
by =1− P
E
. The following rules are applied during the
propagation of STPs.
1) If there is no output-signal-transition (output keeps its
logic value), then the deviation on the output net is 0.
2) If there are multiple inputs that can cause the expected
signal-transition at the output of a gate, only the input-
to-output path that causes the highest deviation at the
output net is considered. The other inputs are treated as
if they have no effect on the deviation calculation (i.e.,
they are held at the non-controlling value).
3) When multiple inputs are required to change at the
same time to provide the expected output transition,
all required input-to-output paths of the gate are con-
sidered. Only the unnecessary (redundant) paths are
discarded.
A key premise of this paper is that output deviations can be
used to compare path lengths. As in the case of path delays, the
net deviations also increase as the signal propagates through
a sensitized path, a property that follows from the rules used
to calculate STPs for a gate output. This claim is formally
proven next.
Lemma 1: For any net, let the STP vector be given by
<P
L→L
,P
L→H
,P
H→L
,P
H→H
>. Among these four prob-
abilities, i.e., <P
L→L
,P
L→H
,P
H→L
,P
H→H
>, at least one
is non-zero and at most two can be non-zero.
Proof: If there is no signal-value change (the event L →
L or H → H ), the expected STP is 1 and all other probabilities
are 0. If there is a signal-value change, only the expected
signal-transition events and the delay-fault case have non-zero
probabilities associated with them. The delay-fault case for an
expected signal value change of L → H is L → L (the signal
value does not change because of a delay-fault). Similarly, the
delay-fault case for an expected signal value change of H → L
is H → H.
Theorem 1: The deviation on a net always increases or
stays constant on a sensitized path if the signal-probability
propagation rules are applied.
Proof: Consider a gate with K inputs and one output.
The signal-transition on the output net depends on one of the
following cases. From Lemma 1, we note that only two cases
need to be considered.
1) Only one of the input-port signal-transitions is enough
to create the output signal-transition.
2) Multiple input-port signal-transitions are required to
create the output signal-transition.
Let P
OUT,j
be the probability that the gate output makes the
expected signal-transition for a given pair of patterns on input
j, where 1 ≤ j ≤ K. Let
OUT,j
=1− P
OUT,j
be the deviation
for the net corresponding to the gate output.
1) Case (i): Consider a signal-transition on input j. Let
Q
j
be the probability of occurrence of this transition. Let d
j
be the entry in the gate’s DDPM that corresponds to the given
signal-transition on j. The probability that the output makes a
signal-transition is given by
P
OUT,j
= Q
j
(1 − d
j
). (2)
We assume here that an error at a gate input is independent
from the error introduced by the gate. Note that P
OUT,j
≤ Q
j
since 0 ≤ d
j
≤ 1. Therefore, the probability of getting
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764 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 5, MAY 2010
Fig. 2. Example to illustrate the propagation of STPs through the gates of
a logic circuit.
TABLE II
Example DDPM for AND, XOR, INV
Initial Input State
AND prob
00 01 10
11
Inputs
IN0
0.2
0.3 0
0.2
IN1 0 0.2 0.3
XOR prob 00 01
10 11
Inputs
IN0 0.3 0.4
0.1 0.2
IN1
0.3 0.4 0.2 0.4
INV prob 0 1
Inpus
IN0 0.2 0.2
the expected signal-transition decreases and the deviation
OUT,j
=1− P
OUT,j
increases (or does not change) as we
pass through a gate on a sensitized path. The overall output
deviation
∗
OUT
on the output net is calculated as
∗
OUT
= max
i≤j≤K
{
OUT,j
}. (3)
2) Case (ii): Suppose L input ports (L>1), indexed 1,
2, ..., L, are required to make a transition for the gate output
to change. Let d
∗
max
= max
1≤j≤L
{d
j
}. The output deviation for
the gate in this case is defined as
∗
OUT
=
L
i=1
P
OUT,i
· (1 − d
∗
max
). (4)
Note that
∗
OUT
≤ P
OUT,i
, 1 ≤ i ≤ L, since 0 ≤ d
∗
max
≤ 1.
Therefore, we conclude that the probability of getting
the expected transition on a net either decreases or remains
the same as we pass through a logic gate. In other words, the
deviation is monotonically non-decreasing along a sensitized
path.
Example: Fig. 2 shows STPs and their propagation for
a simple circuit. The test stimuli and the expected fault-free
transitions on each net are shown in dark boxes. The calculated
STPs are shown in angled brackets (...). The DDPMs of
the gates (OR, AND, XOR, and INV) used in this circuit are
given in Tables I and II. The entries in both tables are chosen
arbitrarily.
In the following example, the deviations are calculated
based on the rules mentioned above for the example circuit
in Fig. 2.
1) Net E: There is no output change, which implies that E
has the STP 1, 0, 0, 0.
2) Net F: The output changes due to IN1 (net D) of XOR.
There is a DDP of 0.4. It implies that with a probability
of 0.4, the output will stay at LOW value, i.e., the STP
for net F is 0.4, 0.6, 0, 0.
3) Net G: Output changes due to IN0 (net D) of INV, i.e.,
the STP for net G is 0.2, 0.8, 0, 0.
4) Net H: Output changes due to IN1 (net F) of OR.
a) If IN1 stays at LOW, output does not change.
Therefore, the STP for net H is 0.4 1, 0, 0, 0,
where denotes the dot product.
b) If IN1 goes to HIGH, output changes with a
DDP of 0.2, i.e., the STP for net H is 0.6
0.2,
0.8, 0, 0.
c) Combining all the above cases, the STP for net H
is 0.52 , 0.48.0, 0.
5) Net J: Output changes due to both IN0 (net F) and IN1
(net G) of AND (both required).
a) If both stay at LOW, output does not change, which
implies that J has the STP 0.4 0.21, 0, 0, 0.
b) If one of them stays at LOW, output does
not change, i.e., the STP for net J is 0.4
0.81, 0, 0, 0 +0.6 0.21, 0, 0, 0.
c) If both go to HIGH, the output changes with
a DDP. Since both inputs change, we use the
maximum DDP, i.e., the STP for net J is 0.6
0.8 0.3,
0.7, 0, 0.
d) Combining all the above cases, the STP for net J
is 0.664, 0.336, 0, 0.
6) Net Q1: The output changes due to only one of the inputs
of OR. We need to calculate the deviation for both cases
and select the one that causes maximum deviation at the
output (Q1).
a) For IN0 (net H) of OR.
i) If IN0 stays at LOW, the output does not
change, i.e., the STP for net Q1 is 0.52
1, 0, 0, 0.
ii) If IN0 goes to HIGH, the output changes
with a DDP, i.e., the STP for net Q1 is
0.48 0.5, 0.5, 0, 0.
iii) Combining all the above cases, the STP for net
Q1 is 0.76, 0 .24 , 0, 0.
b) For IN1 (net J) of OR.
i) If IN1 stays at LOW, the output does not
change, i.e., the STP for net Q1 is 0.664
1
, 0, 0, 0.
ii) If IN1 goes to HIGH, the output changes with
a DDP, i.e., the STP for net Q1 is 0.336
0.2, 0.8, 0, 0.
iii) Combining all the above cases, the STP for net
Q1 is 0.7312, 0.2688, 0, 0.
c) Since IN0 provided the higher deviation, we
finally conclude that the STP for net Q1 is
0.76, 0.24, 0, 0.
Hence, the deviation on Q1 is 0.76.
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