Proceedings ArticleDOI
ALAPTF: a new transition fault model and the ATPG algorithm
P. Gupta,Michael S. Hsiao +1 more
- pp 1053-1060
TLDR
A new transition fault model called as late as possible transition fault (ALAPTF) model, which is capable of detecting smaller gate delays and produces better results in case of process variations is presented.Abstract:
The work presents a new transition fault model called as late as possible transition fault (ALAPTF) model. The model aims at detecting smaller delays, which be missed by both the traditional transition fault model and the path delay model. The model makes sure that each transition is launched as late as possible at the fault site, accumulating the small delay defects along its way. Because some transition faults may require multiple paths to be launched, the simple path-delay model miss such faults. Results on ISCAS'85 and ISCAS'89 benchmark circuits shows that for all the cases, the new model is capable of detecting smaller gate delays and produces better results in case of process variations. For all circuits, on an average, 30% of the time the transition reaches later than traditional models. The algorithm proposed also detects robust and non-robust paths along with the transition faults and the execution time is linear to the circuit size.read more
Citations
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Proceedings ArticleDOI
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects
Xijiang Lin,Kun-Han Tsai,Chen Wang,M. Kassab,Janusz Rajski,Takeo Kobayashi,Randy Klingenberg,Y. Sato,S. Hamada,Takashi Aikyo +9 more
TL;DR: The experimental results show that significant test quality improvement is achieved when applying timing-aware ATPG with DSM to industrial designs.
Proceedings ArticleDOI
Timing-based delay test for screening small delay defects
TL;DR: An improved pattern generation technique for transition fault model, which provides a higher coverage of small delay defect that lie along the long paths, using a commercial no-timing ATPG tool.
Journal ArticleDOI
Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits
TL;DR: A test-grading technique that uses the method of output deviations for screening small-delay defects (SDDs) and a new gate-delay defect probability measure is defined to model delay variations for nanometer technologies.
Proceedings ArticleDOI
Supply Voltage Noise Aware ATPG for Transition Delay Faults
TL;DR: A novel method to measure the average power of at-speed test patterns, referred to as switching cycle average power (SCAP) is proposed, and a new practical framework is proposed to generate supply noise tolerant delay test patterns to significantly reduce the supply noise.
References
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Numerical Recipes in FORTRAN - The Art of Scientific Computing - Second Edition
TL;DR: This paper presents a list of recommended recipes for making CDRom decks and some examples of how these recipes can be modified to suit theommelier's needs.
Journal ArticleDOI
Numerical recipes in C. The art of scientific computing
Proceedings Article
Model for Delay Faults Based Upon Paths
TL;DR: A procedure is described which identifies paths which are tested for path faults by a set of patterns, independent of the delays of any individual gate of the network, which is a global delay fault model.
Journal ArticleDOI
Scan-based transition test
Jacob Savir,S. Patil +1 more
TL;DR: In this paper, several issues of skewed-load transition test are investigated, such as transition test calculus, detection probability of transition faults, transition fault coverage, and enhancement of transition test quality.