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Vlsi Digital Signal Processing Systems: Design And Implementation
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TLDR
This book discusses Digital Signal Processing Systems, Pipelining and Parallel Processing, Synchronous, Wave, and Asynchronous Pipelines, and Bit-Level Arithmetic Architectures.Abstract:
Introduction to Digital Signal Processing Systems. Iteration Bound. Pipelining and Parallel Processing. Retiming. Unfolding. Folding. Systolic Architecture Design. Fast Convolution. Algorithmic Strength Reduction in Filters and Transforms. Pipelined and Parallel Recursive and Adaptive Filters. Scaling and Roundoff Noise. Digital Lattice Filter Structures. Bit-Level Arithmetic Architectures. Redundant Arithmetic. Numerical Strength Reduction. Synchronous, Wave, and Asynchronous Pipelines. Low-Power Design. Programmable Digital Signal Processors. Appendices. Index.read more
Citations
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Journal ArticleDOI
An Efficient LUT Design on FPGA for Memory-Based Multiplication
C. S. Vinitha,R. K. Sharma +1 more
TL;DR: An efficient Lookup Table (LUT) design for memory-based multiplier that occupies nearly 62% less area in terms of number of slices as compared to the OMS design and the maximum path delay is decreased by 77% for a 64-bit input.
Proceedings ArticleDOI
Architecture for area-efficient 2-D transform in H.264/AVC
TL;DR: This paper explores algorithms and architectures for the 2-D transform in H.264/AVC, of which the operations are very simple (i.e. only shift and add), and shows that fewer operations do not always result in more compact designs.
Journal ArticleDOI
A novel framework for retiming using evolutionary computation for high level synthesis of digital filters
Deepa Yagain,A. Vijayakrishna +1 more
TL;DR: The designed novel algorithm is for the synthesis of high speed digital filters for different signal processing applications based on nature inspired evolutionary computation method and gives optimality in terms of algorithm processing speed and digital filter operating frequency with register count as a constraint.
Journal ArticleDOI
Different retiming transformation technique to design optimized low power VLSI architecture
S. Jalaja,Vijaya Prakash A M +1 more
TL;DR: A different method for designing low power retime architecture is presented, and retiming transformation is extended in two-ways to reduce the power consumption of the design.
Journal ArticleDOI
Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic
TL;DR: The complexity analysis reveals that the area complexity of different units of DA FIR filter structure does not increase proportionately with the level of parallelism, and an appropriate selection of LUT decomposition factor could improve the area-delay efficiency of both fixed- coefficient and variable-coefficient DA-based FIR structures.
References
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Journal ArticleDOI
VLSI Array processors
TL;DR: A general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives is provided in this article, where a broad range of application domains including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing.
ReportDOI
VLSI Array Processor
TL;DR: Detailed design of the Arithmetic Processor Unit (APU) chip has been completed and all cell types have been run through the design rule check (DRC) programs, corrected and verified.
Book
VLSI Synthesis of DSP Kernels: Algorithmic and Architectural Transformations
TL;DR: This paper presents a framework for Algorithmic and Architectural Transformations for Multiplication-Free Linear Transforms and some examples of how this framework has been applied to DSP implementation.