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Vlsi Digital Signal Processing Systems: Design And Implementation
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TLDR
This book discusses Digital Signal Processing Systems, Pipelining and Parallel Processing, Synchronous, Wave, and Asynchronous Pipelines, and Bit-Level Arithmetic Architectures.Abstract:
Introduction to Digital Signal Processing Systems. Iteration Bound. Pipelining and Parallel Processing. Retiming. Unfolding. Folding. Systolic Architecture Design. Fast Convolution. Algorithmic Strength Reduction in Filters and Transforms. Pipelined and Parallel Recursive and Adaptive Filters. Scaling and Roundoff Noise. Digital Lattice Filter Structures. Bit-Level Arithmetic Architectures. Redundant Arithmetic. Numerical Strength Reduction. Synchronous, Wave, and Asynchronous Pipelines. Low-Power Design. Programmable Digital Signal Processors. Appendices. Index.read more
Citations
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Journal Article
Pipelined architectures for the Frequency Domain linear equalizer
TL;DR: Novel pipelined architectures for the implementation of the frequency domain linear equalizer are presented and are suitable for implementation on special purpose hardware by means of the ASIC, ASIP or FPGA VLSI processors.
Proceedings ArticleDOI
Exploitation of instruction-level parallelism for optimal loop scheduling
TL;DR: A linear programming implementation produces an optimum loop schedule, making the technique applicable to production compilation and hardware parametrization and can provide faster loop schedules and a significant reduction of the problem complexity and solution time.
Book ChapterDOI
FPGA Implementation of Adaptive Filtering Algorithms for Noise Cancellation—A Technical Survey
Pankaj Goel,Mahesh Chandra +1 more
TL;DR: It has been observed that the performance of various adaptive filter structures varies considerably in terms of rate of convergence, throughput rate, improvement in signal-to-noise ratio (SNR), maximum clock speed, hardware complexity, power consumption and cost.
Book ChapterDOI
Embedded Context Aware Hardware Component Generation for Dataflow System Exploration
TL;DR: A technique for overcoming system level inflexibility with both pre-designed intellectual property cores and most customized component creation techniques is presented, by allowing flexible circuit architectures to be created that can be optimized as desired, providing increased throughput with no extra resource usage in some situations.
Dissertation
Arithmetic recodings for ECC cryptoprocessors with protections against side-channel attacks
TL;DR: A study is conducted at the hardware level to provide an ECC cryptosystem with a regular behaviour of computed operations during the scalar multiplication so as to protect against some side-channel attacks.
References
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Journal ArticleDOI
VLSI Array processors
TL;DR: A general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives is provided in this article, where a broad range of application domains including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing.
ReportDOI
VLSI Array Processor
TL;DR: Detailed design of the Arithmetic Processor Unit (APU) chip has been completed and all cell types have been run through the design rule check (DRC) programs, corrected and verified.
Book
VLSI Synthesis of DSP Kernels: Algorithmic and Architectural Transformations
TL;DR: This paper presents a framework for Algorithmic and Architectural Transformations for Multiplication-Free Linear Transforms and some examples of how this framework has been applied to DSP implementation.