Open AccessBook
Vlsi Digital Signal Processing Systems: Design And Implementation
Reads0
Chats0
TLDR
This book discusses Digital Signal Processing Systems, Pipelining and Parallel Processing, Synchronous, Wave, and Asynchronous Pipelines, and Bit-Level Arithmetic Architectures.Abstract:
Introduction to Digital Signal Processing Systems. Iteration Bound. Pipelining and Parallel Processing. Retiming. Unfolding. Folding. Systolic Architecture Design. Fast Convolution. Algorithmic Strength Reduction in Filters and Transforms. Pipelined and Parallel Recursive and Adaptive Filters. Scaling and Roundoff Noise. Digital Lattice Filter Structures. Bit-Level Arithmetic Architectures. Redundant Arithmetic. Numerical Strength Reduction. Synchronous, Wave, and Asynchronous Pipelines. Low-Power Design. Programmable Digital Signal Processors. Appendices. Index.read more
Citations
More filters
Proceedings ArticleDOI
A 7GS/s, 1.2 V. pseudo logic encoder based flash ADC using TIQ technique
TL;DR: A new digital encoder network called the Pseudo- dynamic NMOS encoder is proposed to be used in the proposed TIQ based architecture of flash ADC, which outperforms all of the existing encoding networks.
Proceedings Article
Area-Efficient Linear Regression Architecture for Real-Time Signal Processing on FPGAs
TL;DR: Different hardware architectures for the implementation of the linear regression method on FPGAs, specially targeting area restrictive systems, are proposed, meeting the hard real-time constraints this kind of systems have.
Journal Article
Application of Modified Distributed Arithmetic Concept in FIR Filter Implementations Targeted at Heterogeneous FPGAs
Michal Staworko,Mariusz Rawski +1 more
TL;DR: The paper presents an application of modified distributed arithmetic concept that allows for very efficient implementation of FIR filters in heterogeneous FPGA architectures.
Journal ArticleDOI
A multi-stage fault-tolerant multiplier with triple module redundancy (TMR) technique
TL;DR: This study proposes a multistage fault-tolerant (MSFT) scheme for fixed-width array multipliers that divide the array multiplier into multiple stages, and implement a single processing element (PE) by regarding multiple computation cycles to achieve a low area design.
Proceedings ArticleDOI
A novel architecture for Walsh Hadamard transforms using distributed arithmetic principles
TL;DR: In this article, a novel architecture for the Fast Hadamard Transform, using distributed arithmetic techniques, is proposed and the associated design using both a distributed arithmetic ROM and Accumulator structure and a sparse matrix factorisation technique.
References
More filters
Journal ArticleDOI
VLSI Array processors
TL;DR: A general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives is provided in this article, where a broad range of application domains including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing.
ReportDOI
VLSI Array Processor
TL;DR: Detailed design of the Arithmetic Processor Unit (APU) chip has been completed and all cell types have been run through the design rule check (DRC) programs, corrected and verified.
Book
VLSI Synthesis of DSP Kernels: Algorithmic and Architectural Transformations
TL;DR: This paper presents a framework for Algorithmic and Architectural Transformations for Multiplication-Free Linear Transforms and some examples of how this framework has been applied to DSP implementation.