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Vlsi Digital Signal Processing Systems: Design And Implementation
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TLDR
This book discusses Digital Signal Processing Systems, Pipelining and Parallel Processing, Synchronous, Wave, and Asynchronous Pipelines, and Bit-Level Arithmetic Architectures.Abstract:
Introduction to Digital Signal Processing Systems. Iteration Bound. Pipelining and Parallel Processing. Retiming. Unfolding. Folding. Systolic Architecture Design. Fast Convolution. Algorithmic Strength Reduction in Filters and Transforms. Pipelined and Parallel Recursive and Adaptive Filters. Scaling and Roundoff Noise. Digital Lattice Filter Structures. Bit-Level Arithmetic Architectures. Redundant Arithmetic. Numerical Strength Reduction. Synchronous, Wave, and Asynchronous Pipelines. Low-Power Design. Programmable Digital Signal Processors. Appendices. Index.read more
Citations
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Proceedings ArticleDOI
Design and implementation of area efficient 2-parallel filters on FPGA using image system
L Kholee Phimu,Manoj Kumar +1 more
TL;DR: The design of area-efficient 2-parallel FIR filter is shown using VHDL and its implementation on FPGA using image system and its simulation using Xilinx 14.2 are discussed.
Proceedings ArticleDOI
Hardware Obfuscation of Digital FIR Filters
TL;DR: Experimental results show that the proposed technique can lead to filter designs with competitive hardware complexity and higher resiliency to attacks with respect to previously proposed methods.
Journal ArticleDOI
Design and Implementation of Encoder for (15, k) Binary BCH Code Using VHDL and eliminating the fan-out
TL;DR: This paper has designed and implemented a BCH Encoder on FPGA using VHDL for reliable data transfers in AWGN channel with multiple error correction control and a comparative performance based on synthesis & simulation onFPGA is presented.
Proceedings ArticleDOI
Implementation of efficient parallel discrete cosine transform using stochastic logic
Yan Li,Jianhao Hu,Jie Chen +2 more
TL;DR: A new area-saving parallel DCT design is provided to improve the system throughput by using the proposed stochastic OR-adder and OR-AND-adder to meet the requirement of image processing while maintaining a ± 5% performance difference compared to the traditional DCT implementation.
Journal ArticleDOI
Block Fast FIR Algorithm and Circuit Design
TL;DR: A 128 order configurable FIR filter circuit with 16 order as a block based on fast fir algorithm (FFA), block FFA (BFFA) is proposed, and the analysis of experimental data shows that the 16 bit integer FIR filter performance reaches 881.78Gop/s.
References
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Journal ArticleDOI
VLSI Array processors
TL;DR: A general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives is provided in this article, where a broad range of application domains including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing.
ReportDOI
VLSI Array Processor
TL;DR: Detailed design of the Arithmetic Processor Unit (APU) chip has been completed and all cell types have been run through the design rule check (DRC) programs, corrected and verified.
Book
VLSI Synthesis of DSP Kernels: Algorithmic and Architectural Transformations
TL;DR: This paper presents a framework for Algorithmic and Architectural Transformations for Multiplication-Free Linear Transforms and some examples of how this framework has been applied to DSP implementation.