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Vlsi Digital Signal Processing Systems: Design And Implementation
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TLDR
This book discusses Digital Signal Processing Systems, Pipelining and Parallel Processing, Synchronous, Wave, and Asynchronous Pipelines, and Bit-Level Arithmetic Architectures.Abstract:
Introduction to Digital Signal Processing Systems. Iteration Bound. Pipelining and Parallel Processing. Retiming. Unfolding. Folding. Systolic Architecture Design. Fast Convolution. Algorithmic Strength Reduction in Filters and Transforms. Pipelined and Parallel Recursive and Adaptive Filters. Scaling and Roundoff Noise. Digital Lattice Filter Structures. Bit-Level Arithmetic Architectures. Redundant Arithmetic. Numerical Strength Reduction. Synchronous, Wave, and Asynchronous Pipelines. Low-Power Design. Programmable Digital Signal Processors. Appendices. Index.read more
Citations
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Proceedings ArticleDOI
Low power design of vlsi circuits and systems
Peiyi Zhao,Zhongfeng Wang +1 more
TL;DR: This paper first gives a brief overview for low power optimization techniques at system and architecture level, then focuses discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems.
Journal ArticleDOI
Performance of CSE Techniques for Designing Multiplier-Less FIR Filter Using Evolutionary Algorithms
TL;DR: An efficient design of multiplier-less digital finite impulse response (FIR) filter is presented, where the sub-expression elimination (SE) algorithms are employed on filter coefficients, and optimization is done with evolutionary algorithms.
Journal ArticleDOI
High-throughput turbo decoder using pipelined parallel architecture and collision-free interleaver
TL;DR: The present work has demonstrated that a 32 maximum a posteriori probability (MAP) decoder core achieves a data rate of 1.138 Gbps at a maximum clock frequency of 486 MHz when implemented in a 90 nm process technology.
Dissertation
Circuit implementations for high-efficiency video coding tools
TL;DR: Digital circuits for two HEVC tools - inverse transform and deblocking filter are implemented to support Quad-Full HD (4K x 2K) video decoding at 30fps.
Journal ArticleDOI
Winograd Convolution for Deep Neural Networks: Efficient Point Selection
TL;DR: It is shown that it is not necessary to choose integers or simple fractions as evaluation points, and that lower errors can be achieved with non-obvious real-valued points, as well as a range of sizes for small convolutions, and a novel approach to point selection.
References
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Journal ArticleDOI
VLSI Array processors
TL;DR: A general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives is provided in this article, where a broad range of application domains including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing.
ReportDOI
VLSI Array Processor
TL;DR: Detailed design of the Arithmetic Processor Unit (APU) chip has been completed and all cell types have been run through the design rule check (DRC) programs, corrected and verified.
Book
VLSI Synthesis of DSP Kernels: Algorithmic and Architectural Transformations
TL;DR: This paper presents a framework for Algorithmic and Architectural Transformations for Multiplication-Free Linear Transforms and some examples of how this framework has been applied to DSP implementation.