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Vlsi Digital Signal Processing Systems: Design And Implementation
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TLDR
This book discusses Digital Signal Processing Systems, Pipelining and Parallel Processing, Synchronous, Wave, and Asynchronous Pipelines, and Bit-Level Arithmetic Architectures.Abstract:
Introduction to Digital Signal Processing Systems. Iteration Bound. Pipelining and Parallel Processing. Retiming. Unfolding. Folding. Systolic Architecture Design. Fast Convolution. Algorithmic Strength Reduction in Filters and Transforms. Pipelined and Parallel Recursive and Adaptive Filters. Scaling and Roundoff Noise. Digital Lattice Filter Structures. Bit-Level Arithmetic Architectures. Redundant Arithmetic. Numerical Strength Reduction. Synchronous, Wave, and Asynchronous Pipelines. Low-Power Design. Programmable Digital Signal Processors. Appendices. Index.read more
Citations
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Journal ArticleDOI
Hardware Efficient Approach for Memoryless-Based Multiplication and Its Application to FIR Filter
Jianjun He,Jiafeng Xie +1 more
TL;DR: The design optimization of onedimensional and two-dimensional fully systolic arrays for area-delay-efficient implementation of finite impulse response (FIR) filter, using the proposed memoryless-based multiplier is presented.
Proceedings ArticleDOI
A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA
TL;DR: In this article, an FPGA-based reconfigurable accelerator for efficient GAN training is proposed, where the cascaded fast FIR algorithm (CFFA) is opti-mized towards GAN learning, and a fast convolution processing element (FCPE) based on the optimized algorithm is introduced to support various computation patterns during GGAN training.
Proceedings ArticleDOI
A compact DSP core with static floating-point unit & its microcode generation
TL;DR: This paper proposes a compact DSP core for dual-core multimedia SoC and its complete software development tools that contains a dataflow engine that is composed of off-the-shelf memory modules with limited ports and is equipped with novel static floating-point units to emulate expensive floating- point DSP operations at low cost.
Proceedings ArticleDOI
Electronic Equalization of Fiber Optic Links
TL;DR: In this paper, the authors provide an overview of some of the driving factors that limit the performance of optical links and provide a design example of an MLSE-based receiver for 10 Gb/sec long haul links.
Proceedings ArticleDOI
On Derivation of the Winograd Discrete Fourier Transform Algorithms for N Equal to the Power of Two
TL;DR: A simple, understandable and fairly unified approach to the derivation of the Winograd DFT algorithms for the case N = 8 is used and it is easy to verify that algorithms for other lengths of sequences that are powers of two can be synthesized in a similar way.
References
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Journal ArticleDOI
VLSI Array processors
TL;DR: A general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives is provided in this article, where a broad range of application domains including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing.
ReportDOI
VLSI Array Processor
TL;DR: Detailed design of the Arithmetic Processor Unit (APU) chip has been completed and all cell types have been run through the design rule check (DRC) programs, corrected and verified.
Book
VLSI Synthesis of DSP Kernels: Algorithmic and Architectural Transformations
TL;DR: This paper presents a framework for Algorithmic and Architectural Transformations for Multiplication-Free Linear Transforms and some examples of how this framework has been applied to DSP implementation.