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Vlsi Digital Signal Processing Systems: Design And Implementation
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TLDR
This book discusses Digital Signal Processing Systems, Pipelining and Parallel Processing, Synchronous, Wave, and Asynchronous Pipelines, and Bit-Level Arithmetic Architectures.Abstract:
Introduction to Digital Signal Processing Systems. Iteration Bound. Pipelining and Parallel Processing. Retiming. Unfolding. Folding. Systolic Architecture Design. Fast Convolution. Algorithmic Strength Reduction in Filters and Transforms. Pipelined and Parallel Recursive and Adaptive Filters. Scaling and Roundoff Noise. Digital Lattice Filter Structures. Bit-Level Arithmetic Architectures. Redundant Arithmetic. Numerical Strength Reduction. Synchronous, Wave, and Asynchronous Pipelines. Low-Power Design. Programmable Digital Signal Processors. Appendices. Index.read more
Citations
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Proceedings ArticleDOI
Efficient fast convolution architectures for convolutional neural network
TL;DR: A fully parallel architecture with high throughput based on the fast convolution algorithm and its matrix form is proposed and output data reuse scheme corresponding to CNN is considered to further increase efficiency and reduce computation redundancy.
Proceedings ArticleDOI
DSP architecture optimization in Matlab/Simulink environment
TL;DR: An automated architecture optimization for DSP algorithms within graphical Matlab/Simulink environment is proposed and produces optimal architectures with energy efficiency of 5GOPS/mW in a 90 nm CMOS technology.
Proceedings ArticleDOI
Low-complexity modified Mastrovito multipliers over finite fields GF(2/sup M/)
Leilei Song,Keshab K. Parhi +1 more
TL;DR: This paper considers the design of low-complexity dedicated finite field multipliers and proposes a modified Mastrovito multiplication scheme, which has a complexity proportional to (m-1-pwt), where pwt is the Hamming weight of the underlying irreducible polynomial.
Proceedings ArticleDOI
Efficient sharpening of CIC decimation filter
TL;DR: An efficient sharpening of a CIC decimation filter for an even decimation factor is proposed and the sharpened filter is of length that is half of that of the original CIC filter.
Journal ArticleDOI
Low-Latency High-Throughput Systolic Multipliers Over $GF(2^{m})$ for NIST Recommended Pentanomials
TL;DR: This is the first report on low-latency systolic multipliers for finite fields where latency is independent of field-order and it is shown that the proposed multipliers have significantly lower latency and higher throughput than the existing designs.
References
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Journal ArticleDOI
VLSI Array processors
TL;DR: A general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives is provided in this article, where a broad range of application domains including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing.
ReportDOI
VLSI Array Processor
TL;DR: Detailed design of the Arithmetic Processor Unit (APU) chip has been completed and all cell types have been run through the design rule check (DRC) programs, corrected and verified.
Book
VLSI Synthesis of DSP Kernels: Algorithmic and Architectural Transformations
TL;DR: This paper presents a framework for Algorithmic and Architectural Transformations for Multiplication-Free Linear Transforms and some examples of how this framework has been applied to DSP implementation.