VLSI Implementation of a High-Throughput Iterative Fixed-Complexity Sphere Decoder

TLDR: A soft-input soft-output fixed-complexity-sphere-decoding algorithm and its very large scale integration architecture are proposed for the iterative MIMO receiver and its deeply pipelined architecture improves the detection performance significantly with low detection latency.

Abstract: By exchanging soft information between the multiple-input multiple-output (MIMO) detector and the channel decoder, an iterative receiver can significantly improve the performance compared to the noniterative receiver. In this brief, a soft-input soft-output fixed-complexity-sphere-decoding algorithm and its very large scale integration architecture are proposed for the iterative MIMO receiver. The deeply pipelined architecture employs the optimized hybrid enumeration to search for the best child node estimate efficiently. By adding the counter hypotheses in parallel with other candidates, the proposed iterative MIMO detector improves the detection performance significantly with low detection latency. An iterative detector for an 4 × 4 64-quadrature amplitude modulation (QAM) MIMO system based on our proposed architecture is designed and implemented using the 90-nm CMOS technology. The detector can achieve a maximum throughput of 2.2 Gbit/s with an area efficiency of 3.96 Mbit/s/kGE, which is more efficient than other iterative MIMO detectors.