Proceedings ArticleDOI
X-compact: an efficient response compaction technique for test cost reduction
Subhasish Mitra,Kee Sup Kim +1 more
- pp 311-320
TLDR
This work presents a technique for compacting test response data using combinational logic circuits that enables up to an exponential reduction in the number of pins required to collect test response from a chip.Abstract:
We present a technique for compacting test response data using combinational logic circuits. Our compaction technique enables up to an exponential reduction in the number of pins required to collect test response from a chip. The combinational circuits require negligible area, do not add any extra delay during normal operation, guarantee detection of defective chips even in the presence of sources of unknown logic values (often referred to as Xs) and preserve diagnosis capabilities for all practical scenarios. The technique has minimum impact on current design and test flows, and can be used to reduce test time, test data volume, test-I/O pins and tester channels, and also to improve test quality.read more
Citations
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Journal ArticleDOI
Embedded deterministic test
TL;DR: This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.
Proceedings ArticleDOI
Convolutional compaction of test responses
TL;DR: A finite memory compactor called convolutional compactor that provides compaction ratios of test responses in excess of 100x even for a very small number of outputs and the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses is introduced.
Proceedings ArticleDOI
Post-silicon validation opportunities, challenges and recent advances
TL;DR: An overview of the post-silicon validation problem and how it differs from traditional pre- silicon verification and manufacturing testing is provided.
Proceedings ArticleDOI
Channel masking synthesis for efficient on-chip test compression
TL;DR: This work describes a simple but cost-effective solution called channel masking that masks the X-states and allows test compression methods to be widely deployed on a variety of designs.
Proceedings ArticleDOI
Application of Saluja-Karpovsky compactors to test responses with many unknowns
TL;DR: This paper addresses the problem of compacting test responses in the presence of unknowns at the input of the compactor by exploiting the capabilities of well-known error detection and correction codes by using Saluja-Karpovsky Space Compactors.
References
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Proceedings ArticleDOI
OPMISR: the foundation for compressed ATPG vectors
Carl F. Barnhart,V. Brunkhorst,Frank O. Distler,O. Farnsworth,Brion L. Keller,Bernd Karl Ferdinand Koenemann +5 more
TL;DR: Techniques are presented in this paper that allow for substantial compression of Automatic Test Pattern Generation (ATPG) produced test vectors, allowing for a more than 10-fold reduction in tester scan buffer data volume on ATPG compacted tests.
Proceedings ArticleDOI
Reducing test application time for full scan embedded cores
Ilker Hamzaoglu,Janak H. Patel +1 more
TL;DR: In this article, the authors proposed a parallel serial full scan (PSFS) technique for reducing the test application time for full scan embedded cores, which divides the scan chain into multiple partitions and shifts in the same vector to each scan chain through a single scan in input.
Reducing test application time for full scan embeded cores
TL;DR: A new design for testability technique, Parallel Serial Full Scan (PSFS), for reducing the test application time for full scan embedded cores by dividing the scan chain into multiple partitions and shifting in the same vector to each scan chain through a single scan in input.
Book
Logic Design Principles: With Emphasis on Testable Semicustom Circuits
TL;DR: Logic design principles: with emphasis on testable semicustom circuits, Logic design principles with focus on testability semicustomcircuits, and more.
Proceedings ArticleDOI
A SmartBIST variant with guaranteed encoding
Bernd Karl Ferdinand Koenemann,Carl F. Barnhart,Brion L. Keller,Thomas J. Snethen,O. Farnsworth,Donald L. Wheater +5 more
TL;DR: The specific SmartBIST implementation shown in this paper guarantees that all test cubes can be successfully encoded by the modified ATPG algorithm irrespective of the number and position of the care bits.