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How many transistors are in a wafer? 

Wafer backgrinding
Wafer
Wafer dicing
Integrated circuit
Wafer bonding

Answers from top 8 papers

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Papers (8)Insight
Journal Article•DOI
Use of wafer maps in integrated circuit manufacturing
Christian K. Hansen, Poul Thyregod 
01 Jun 1998-Microelectronics Reliability
25 Citations
The wafer yield is a useful measure of the process quality, but other features are necessary to account for.
Journal Article•DOI
Multiple word/bit line redundancy for semiconductor memories
Stanley E. Schuster
01 Oct 1978-IEEE Journal of Solid-state Circuits
205 Citations
Based on a first-pass design of a 16K chip, a significant improvement in the number of usable bits per wafer appears possible.
Proceedings Article•DOI
An innovative chip-to-wafer and wafer-to-wafer stacking
Wei-Chung Lo, Yu-Hua Chen, Jeng-Dar Ko, Tzu-Ying Kuo, Ying-Ching Shih, Su-Tsai Lu 
05 Jul 2006
21 Citations
Compared to the recently research of 3D chip-to-wafer or wafer-to-wafer stacking, it demonstrated of wafer stacking using this reliable design.
Journal Article•DOI
Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors
Sanghyeon Kim, Yuki Ikku, Masafumi Yokoyama, Ryosho Nakane, Jian Li, Yung-Chung Kao, Mitsuru Takenaka, Shinichi Takagi 
29 Jul 2014-Applied Physics Letters
26 Citations
This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost.
Journal Article•DOI
The First Wafer-fused AlGaAs-GaAs-GaN Heterojunction Bipolar Transistor
Sarah Estrada, A. R. Stonas, A. Huntington, Huili Xing, Larry A. Coldren, Steven P. DenBaars, Umesh K. Mishra, Evelyn L. Hu 
01 Jan 2002-MRS Proceedings
5 Citations
This paper reports the first dc device characteristics of a wafer-fused transistor, and demonstrates the potential of wafer fusion for forming electronically active, lattice-mismatched heterojunctions.
Journal Article•DOI
Using a neural network-based approach to predict the wafer yield in integrated circuit manufacturing
Lee-Ing Tong, Wei-I Lee, Chao-Ton Su 
01 Oct 1997-IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part C
13 Citations
In addition, the proposed approach can be written as a computer software to accurately predict the wafer yield in IC manufacturing.
Journal Article•DOI
A process model of wafer thinning by diamond grinding
Chao-Chang A. Chen, Li-Sheng Hsu 
26 May 2008-Journal of Materials Processing Technology
33 Citations
Therefore, the WTPM has been verified in this study and further used for forecasting the limitation of wafer thinning with different wafer thickness.
Journal Article•DOI
Scheduling Cluster Tools for Concurrent Processing of Two Wafer Types
Jun-Ho Lee, Hyun-Jung Kim, Tae-Eog Lee 
17 Jan 2014-IEEE Transactions on Automation Science and Engineering
56 Citations
We also show that, for some special cases, the two wafer types can achieve their maximum throughput rates as if each wafer type exclusively uses the tool regardless of other wafer types in progress.

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