Showing papers on "Analog-to-digital converter published in 1993"

A built-in self-test for ADC and DAC in a single-chip speech CODEC

Abstract: Built-in self-test (BIST) has been applied to test an analog to digital converter (ADC) and a digital to analog converter (DAC) embedded in a DSP-core ASIC. The performance characteristics of the ADC and the DAC designed in according with the CCITT recommendations are measured using BIST. Three characteristics have been evaluated and the measured results have shown good agreement with measured results by conventional tests. In the BIST operation, the DSP-core generates input stimulus and analyzes output response. Therefore, test-time is reduced, analog or mixed-signal test equipment is not needed, and finally, test-cost is reduced compared with conventional test methods. This paper describes the BIST design and evaluational results. >

Bandpass sigma-delta analog-to-digital converter (ADC), method therefor, and receiver using same

Abstract: A bandpass sigma-delta analog-to-digital converter (ADC) (10) includes first (11) and second (12) bandpass sigma-delta modulators, and a digital filter (13) connected to digital outputs thereof. In the illustrated embodiment, the first bandpass sigma-delta modulator (11) is a second-order, single bit bandpass modulator, and the second bandpass sigma-delta modulator (12) is a first-order, multiple-bit modulator. Coefficients in feedback paths of the first (11) and second (12) modulators are derived from a transfer function of the digital filter. In one embodiment, a receiver (50) for a system such as frequency modulation (FM) radio converts an intermediate frequency (IF) analog signal to digital in-phase (I) and quaternary (Q) signals using the bandpass sigma-delta ADC (10).

Timing recovery circuit for synchronous waveform sampling

Abstract: A timing circuit having an analog to digital converter (206) to sample an analog signal, a controlled oscillator for controlling sample times of the analog to digital converter, a circuit (312) to detect pulses in the analog signal, a phase error circuit to subtract one of two samples from the other to create a phase error measurement and a frequency error measurement. The two samples are taken from either side of a pulse. The phase error measurement is used by the controlled oscillator to adjust the sample timing to take samples at desired locations on the pulse. The circuit also contains constant values used to compensate for the pulse being asymmetrical and to compensate for other pulses that occur close to the detected pulse. The circuit also inserts a known frequency in place of the analog signal to establish a frequency of the controlled oscillator.

A low-power 12-b analog-to-digital converter with on-chip precision trimming

Abstract: The design and performance of a 12-b charge redistribution analog-to-digital converter (ADC) is described. The architecture is chosen to minimize power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a 1- mu m CMOS process. It converts at a 200-kHz rate with a power dissipation of 10 mW. >

Differential comparator and analog-to-digital converter comparator bank using the same

Abstract: A fully differential comparator includes a differential signal input, a differential reference input, and a differential signal output. Identical first and second gain stages are used in the differential comparator that each have a first single-ended input, a second single-ended input, and a differential output. The first single-ended inputs from the first and second gain stages form the differential signal input of the differential comparator. The second single-ended inputs from the first and second gain stages form the differential reference input of the differential comparator. The differential outputs of the first and second gain stages are cross-coupled to form the differential signal output of the differential comparator. The differential comparator can be used in conjunction with a conventional resistor string found in the front end of a flash ADC, but in a novel manner that prevents undesirable loading effects, as well as other problems associated with prior art single-ended comparators.

Averaging flash analog-to-digital converter

Abstract: A flash-type analog-to-digital converter (ADC) uses only 2 comparators (114h, 114i, 114j...) coupled to the analog input line to generate a n-bit digital output signal. Each pair of these actual comparators are coupled, in parallel, to 2 pseudocomparators (114j+1, 114j+2, 114j+3...) which provide values representing comparisons of the input signal value to respective reference values between the reference values used by the actual comparators. The output signals of each pair actual comparators are combined in respectively different proportions at each of the pseudocomparators. In this manner, the output signals of the actual comparators are averaged to produce the interstitial comparison values. In one embodiment of the invention, the ADC is implemented in BiCMOS technology with a bipolar differential input stage and a CMOS latching comparator. Signals are distributed from the actual comparators to the pseudocomparators via a pair of resistive ladder networks. In other embodiments of the invention the ADC is implemented in CMOS technology and the pseudocomparators use ratioed transistor widths and ratioed capacitors to proportionally divide the ouptut signals of the actual comparators in order to generate the interstitial ouput values. A final embodiment of the invention combines two averaging flash ADCs to form a novel subranging ADC.

Analog-to-digital converter using parallel DELTA SIGMA modulators

Abstract: An approach is presented for relaxing the oversampling requirements in a DELTA SIGMA modulator based analog-to-digital converter through parallel DELTA SIGMA modulation channels with decimation filtering and modulation by sequences ur(n) and vr(n) derived, for example, from an MxM Hadamard matrix By combining M DELTA SIGMA modulators, each with an oversampling ratio of N, an effective oversampling ratio of approximately NM is achieved with only an M-fold increase in the quantization noise power In the special case of N=1, full-rate analog-to-digital conversion is achieved The individual DELTA SIGMA modulators can be any selected from a large class of popular DELTA SIGMA modulators Unlike most other approaches to trading modulator complexity for accuracy, the system retains the robustness of the individual DELTA SIGMA modulators to circuit imperfections

Folding circuit and analog-to-digital converter

Abstract: By making a folded waveform of a folding circuit sharp, the number of elements used in an ADC is reduced and less power consumption is achieved. A folding circuit is composed of a plurality of master-comparator latches, a pair of wiring means for master-to-slave connection, and a slave latch. By means of the wiring means, the non-inverted outputs and the inverted outputs of the master-comparators latches are alternately drawn in the order of magnitude of reference voltages, superimposed, and fed into a pair of inputs of the slave latch. A Gray code signal is directly encoded by an encoder according to the output of the slave latch. A folded signal, which is the output of the folding circuit, takes a sharp waveform. The number of slave latches can be reduced. No XOR gates are required.

Analog-to-digital converter

Abstract: The present invention discloses an improved analog-to-digital converter. A second sampling circuit samples the voltage difference between an analog signal and a reference voltage, before a first sampling circuit moves to a follow operation from a sample operation. Owing to pipelining by the first and second sampling circuits, even after the first sampling circuit moves to a follow operation, the difference between an analog signal and a reference voltage is still applied to a logical-level amplifier. The output of the logical-level amplifier, amplified to a logical voltage, is converted by a logic device into an A/D conversion output. Therefore, ADC differential non linearity error can be reduced.

Direct digital capture of pulse oximetry waveforms

Abstract: Pulse oximetry sensor photodiodes typically generate a current proportional to the intensity of the pulse oximetry waveforms. This method of waveform capture is prone to electrical noise and requires analog-to-digital conversion downstream for further digital signal processing. This investigation evaluated the use of a light-to-frequency photodiode as an alternative sensor for capturing pulse oximetry waveforms. Red and infrared pulse oximetry waveforms were captured with a Texas Instruments TSL220 light-to-frequency converter. The fidelity of the captured waveforms was excellent. The compact TSL220 combination of photodiode, amplifier, and current-to-frequency converter can potentially replace the light-to-current photodiode, current-to-voltage converter, and analog-to-digital converter now used in typical pulse oximetry applications. >

Method and apparatus for adjusting the sampling phase of a digitally encoded signal in a wireless communication system

Abstract: In a digital wireless communication system, a first unit transmits a digitally encoded signal to a second unit in a plurality of non-contiguous time slots Within each time slot, the digitally encoded signal has a synchronization signal portion followed by a data signal portion The second unit has an antenna to receive the synchronization signal portion of the digitally encoded signal The second unit also has a clock to generate a clock signal at a first rate having a sampling phase An analog to digital converter receives the clock signal and the synchronization signal and samples the synchronization signal at the first rate to generate a first plurality of symbols An interpolator receives the first plurality of symbols and interpolates the first plurality of symbols to generate a second plurality of symbols at a second rate The second rate is a multiple of the first rate A match filter receives the second plurality of symbols and compares the second plurality symbol of symbols to a stored plurality of symbols to generate an error signal The sampling phase of the clock signal is altered in response to the error signal, after to the receipt of the synchronization signal

Analog-to-digital converter with multi-level dither current input

Abstract: An improved sigma-delta analog-to-digital converter (ADC) is disclosed herein. The digital converter includes a dither circuit fabricated within the package of the ADC. The circuit is configured to apply a dither current to the analog input of the ADC. The frequency of the dither current is selected based upon the bandwidth of the analog signals for which the ADC is designed to sample and convert to digital signals. Application of the dither current to the input of the ADC reduces quantization noises produced as a result of certain ranges of DC offset voltages found within analog signals applied to the ADC.

Ripsaw analog-to-digital converter and method

Abstract: An analog-to-digital converter (ADC) generates multiple analog waveforms, preferably as voltage ramps, that progressively increase in signal value over time but at different rates of increase. The ramp with the greatest slope is initially compared with an input signal sample until the ramp exceeds the sample, at which time the system switches to the ramp with the next greatest slope for comparison with the input. The operation then repeats, with the system switching to the next lower ramp each time the current ramp exceeds the input. Both the number of ramp switching events that occur during a sample cycle, and the clock count at the time of the most recent ramp switch, are recorded and used respectively as the most and least significant bits of a digital output. The switching event count proceeds from an initial maximum value from which it subtracts at each switching event, while the clock count builds up from an initial minimum value.

Method and apparatus for high speed analog to digital conversion using multiplexed flash sections

Abstract: Analog to digital conversion of signals at rates higher than can be accomplished by a monolithic flash analog to digital converter is achieved using multiple flash analog to digital converters operated in a parallel architecture. Sample timing of the multiple converters is skewed by selecting subfrequencies of a control clock or different phases of a control clock as the source for the sample control signal. The multiple flash converter outputs are then digitally recombined to produce a single output identical to a flash converter operating at a higher speed than could be obtained for a given set of circuit parameters.

Analog to digital converter

Abstract: Analog audio signals supplied via an analog signal input terminal 1 are translated in parallel via a first ΔΣ modulator 2 and a second ΔΣ modulator 3 into digital audio data which are summed together by an additive node 4. The resulting sum data is attenuated in level by an attenuator 5 and translated by a decimation filter 6 into audio data having a predetermined number of bits and resulting audio data is outputted via an audio data output terminal 7. There is no necessity of providing a decimation filter for each ΔΣ modulator, so that the number of components may be reduced and the circuit may be simplified in construction to lower production costs. Besides, there is no necessity of re-quantizing the audio data at an output stage so that no quantization noise is produced to enable the S/N ratio to be improved by a theoretical value of 3 dB.

Process for the analog-to-digital conversion of microwave signals

Abstract: An optical analog to digital converter for microwave signals in which the input to a Mach-Zehnder modulator/interferometer is split into two branches which are provided with respective laser carrier signals having a difference frequency equal to a desired conversion frequency. An input microwave signal is then used to modulate the carrier signal present in one of the input branches to the interferometer, and the resulting output signal is detected and compared with a predetermined threshold value to generate a binary 1 or 0 output. In a preferred embodiment, a plurality of such interferometers are arranged in a parallel configuration and the modulation of the respective carrier signals is scaled by a factor of two.

Multiplexed delta-sigma analog-to-digital converter

Abstract: An analog-to-digital converter for converting a multitude of analog input signals into a corresponding multitude of digital signals comprises a series arrangement of an analog multiplexer (2), an oversampling sigma-delta modulator (8), a decimator-cum-low-pass filter (10), a digital demultiplexer (12), an interpolator (14) and a digital matrix (16), which are all operated in synchronism.

A 3.6 gigasample/s 5 bit analog to digital converter using 0.3 /spl mu/m AlGaAs-HEMT technology

Abstract: A 0.3 /spl mu/m AlGaAs-HEMT technology was used to develop a high speed analog to digital converter (ADC). The 5-b converter based on a parallel architecture, operates up to a 3.6 GHz sampling rate. Excellent dynamic performance was achieved by an optimized comparator design and careful layout of the signal and clock lines. Each comparator is preceeded by a preamplifier to enhance its sensitivity and to minimize clock kickback. Using source follower buffers at the input, a very linear input capacitance was achieved. Thus the ADC's overall input capacitance is voltage independent. >

Noise source for an analog-to-digital converter

Abstract: A noise source (113 or 217) is coupled to an analog-to-digital converter (115 or 219) so as to remove at least some unwanted spectral components from the analog-to-digital converter (115 or 219) output. In one embodiment, the noise source (113 or 217) is comprised of a sigma-delta digital-to-analog modulator.

Fully parallel superconducting analog-to-digital converter

Abstract: The authors present measurements that follow up on a design of a 3-b wideband analog-to-digital converter (ADC) given by E. Fang et al. (IEEE Trans. Magn., vol.27, no.3, p.2891-4, 1991). The original design has been modified, and some circuit parameters have been changed to optimize the margins. Based on this modified design, the authors have fabricated and were able to demonstrate the functionality not only of simple logic gates, including inverters, AND, OR, NAND, NOR, and XOR, but also of much more complicated combinations, including a complete 2-b ADC and a complete 3-b binary encoder. After a brief description of the design and modifications, low-speed tests of these circuits are presented and discussed. Simulations have shown that the complete 3-b ADC can work up to 5 GHz. >

Method and apparatus for frequency triggering in digital oscilloscopes and the like

Abstract: A data acquisition system includes an analog to digital converter, a computer processor and a waveform memory in which is stored digital data from the A to D converter corresponding to an input signal. The processor provides a trigger responsive to a characteristic of a frequency component or components of the input signal to cause the memory to save the waveform data in the memory. The frequency characteristic may be determined, for example, by carrying out a synchronized recursive discrete Fourier transform which is updated for the selected frequency component or components with each new sample from the A to D converter.

Linear/companding A/D converter

Abstract: A multi-mode analog to digital converter is described for converting an analog input into a digital value according to a linear or a companding transfer function. The converter comprises a comparator, a successive approximation register and a charge redistribution device. The comparator compares the input voltage and a generated voltage. The successive approximation register generates a provisional binary word responsive to the output of the comparator. The charge redistribution device generates the generated voltage according to the provisional binary word and to a selected transfer function. The transfer function may be selected from the group consisting of linear and companding.

CMOS flash analog-to-digital converter with hysteresis

Abstract: A flash analog-to-digital converter has CMOS comparators that compare an analog input signal with internal reference voltages and produce internal output signals. Each comparison is performed according to the threshold voltage of an inverter. A threshold control circuit in each comparator adjusts this threshold voltage according to the internal output signal, thereby providing hysteresis. A logic circuit receives the internal output signals from all the comparators and generates a digital output signal. The hysteresis of the comparators keeps the digital output signal from oscillating between adjacent values when the analog input signal is near one of the internal reference voltages.

Parallel processing based digital matched filter and error detector for a digital demodulator

Abstract: A high chipping rate digital demodulator circuit is coupled to the output of an analog front end communications receiver and comprises a low pass filter in each channel of the receiver. The filtered output is coupled to a plurality of parallel branches each having an analog to digital converter which converts a portion of an analog sample to digital format and effectively reduces the system clock rate by a ratio of the number of parallel branches. One set of parallel branches is coupled to an early-late clock error detector circuits and another set of parallel branches is coupled to data signal detector circuits and then combined before being applied to a clock error processing channel and a data signal phase error channel which maintains the lower clock rate of the parallel branches.

Josephson look-back analog to digital converter

Abstract: A Josephson analog-to-digital (A/D) converter which uses a look-back algorithm to increase accuracy was designed and experimentally verified. The look-back A/D algorithm and its implementation in a Josephson 6-b A/D converter are described. High-speed measurements verified that the 3-b look-back A/D converter functions at 534 Msamples/s. The look-back algorithm increases the margins of an A/D converter that uses the lobes of a superconducting quantum interference device's (SQUID's) threshold curve. The self-gating AND circuits (SGAs) give the A/D converter a short aperture time. The SGAs sample the analog signal in parallel and then the look-back logic decodes the two's complement outputs in series with only one stage of logic per bit. With a stable process the look-back A/D converter can be generated on chip. >

Charge-mode analog to digital converter

Abstract: A symmetric pipelined charge-mode analog to digital converter including a signal-reference CCD channel having a plurality of charge storage stages that are arranged in a serial configuration to carry the signal and reference charges, and a CCD digital channel. A set of two step comparators coupled to the signal-reference channel first senses and stores the signal charge and then senses and compares the reference charge to the signal charge. In the first stage, an initial reference charge is used, and in subsequent stages, an increment of one half the previous stage increment is added to the reference. In addition, at each stage, a charge increment equal to the previous reference increment is conditionally added to the signal charge and a corresponding bit in the digital channel is conditionally set responsive to the comparator. Thus, if the total signal charge is less than the total reference charge at a stage, the charge increment is added to the signal charge in the signal-reference channel, and a corresponding digital bit charge is zeroed in the digital channel. Conversely, if the total signal charge is larger than the told reference charge at a stage, the charge increment is not added to the signal charge and a corresponding digital bit charge is set to represent a one in the digital channel. One configuration provides a differential symmetric architecture wherein two signal-reference channels simultaneously feed a dual symmetric comparator providing enhanced symmetry thereby reducing threshold and offset sensitivity and susceptibility to environmental factors such as ionizing radiation.

Dual range fine/coarse analog to digital converter

Abstract: of EP0567145A method and apparatus for non-linear quantization of a signal that utilizes two or more low-resolution analog to digital converters (ADCs) to allow selective increased quantization levels at desired portions of a signal. This is accomplished by using a primary ADC which provides digital output signals over a first predetermined range, and at least one secondary ADC which provides digital output signals over a smaller predetermined range for the same input values. Accordingly, any secondary ADCs have a smaller quantization step size than the first, and are utilized when finer resolution is desired. The ADCs are kept in alignment by periodically comparing the digital values produced by the ADCs for a known input analog value.

A dual-bit low-offset sigma delta analog-to-digital converter for integrated smart sensors

Abstract: A signal-conditioning circuit is presented which converts the small signal of a thermal-flow sensor into a digital signal. A balanced chopper with bipolar transistors combined with a class B sigma delta converter keeps the offset beneath 10 μV. Although the circuit has been designed especially for a thermal-flow sensor with thermopiles, it is well suited for other small-signal applications.

Fractional channel multichannel analyzer

Abstract: A multichannel analyzer incorporating the features of the present invention obtains the effect of fractional channels thus greatly reducing the number of actual channels necessary to record complex line spectra. This is accomplished by using an analog-to-digital converter in the asynscronous mode, i.e., the gate pulse from the pulse height-to-pulse width converter is not synchronized with the signal from a clock oscillator. This saves power and reduces the number of components required on the board to achieve the effect of radically expanding the number of channels without changing the circuit board.