Showing papers on "Asynchronous communication published in 1980"

Performance Evaluation of Asynchronous Concurrent Systems Using Petri Nets

Abstract: Some analysis techniques for real-time asynchronous concurrent systems are presented. In order to model clearly the synchronization involved in these systems, an extended timed Petri net model is used. The system to be studied is first modeled by a Petri net. Based on the Petri net model, a system is classified into either: 1) a consistent system; or 2) an inconsistent system. Most real-world systems fall into the first class which is further subclassified into i) decision-free systems; ii) safe persistent systems; and iii) general systems. Procedures for predicting and verifying the system performance of all three types are presented. It is found that the computational complexity involved increases in the same order as they are listed above.

The Structure of Parallel Algorithms.

Abstract: Publisher Summary This chapter presents many examples of parallel algorithms and studies them under a uniform framework. The chapter explains a parallel algorithm as a collection of independent task modules that can be executed in parallel and that communicate with each other during the execution of the algorithm. The chapter explains the three important attributes of a parallel algorithm and classifies parallel algorithms in terms of these attributes. Three orthogonal dimensions of the space of parallel algorithms: concurrency control, module granularity, and communication geometry. The classification of parallel algorithms corresponds naturally to that of parallel architectures. Algorithms for synchronous parallel computers are considered, where examples of algorithms using various communication geometries are presented. Algorithms for asynchronous parallel computers are also considered in the chapter. A number of techniques dealing with the difficulties arising from the asynchronous behavior of computation and the examples are mainly drawn from results in concurrent database systems. This chapter deals with the basic issues and techniques in designing parallel algorithms for various architectures. The chapter concludes that issues concerning algorithms for synchronous parallel computers are quite different from those for asynchronous parallel computers.

Serial storage interface apparatus for coupling a serial storage mechanism to a data processor input/output bus

Abstract: Serial storage interface apparatus for coupling a serial storage mechanism, such as a charge coupled storage device or a magnetic bubble storage device, to a data processor input/output (I/O) bus. Speed control circuitry is provided for causing the serial storage mechanism to operate at a higher speed when the data processor is responding more rapidly to data transfer requests from the interface apparatus and at a lower speed when the data processor is responding less rapidly to data transfer requests from the interface apparatus. This speed adjustment feature reduces the amount of data buffering required for interfacing a serial storage mechanism to an asynchronous variable response time I/O bus system.

Asynchronous data transmission system with state variable memory and handshaking protocol circuits

Abstract: This disclosure relates to a system and method for realizing asynchronous sequential circuits in a manner analagous to the stored state method for synchronous sequential circuits. The circuit is a stored state circuit including a memory and an output register with an input line and an input request line coupled to the memory and the output register having an output data line and an output acknowledge line. A pulse generator is coupled to the input request line so as to generate a timing signal, for transmission to the output register, a fixed period of time after receipt of a request signal on the input request line. A request signal will not appear on the input request line until a data signal on the input data line has stabilized. Furthermore, an acknowledge signal will not be generated until a signal on the output data line has stabilized. In this manner, an asynchronous sequential circuit is constructed which allows for utilization of existing component parts and provides for hazard-free and race-free implementations.

Digital communication networks employing speed independent switches

Abstract: An assemblage of digital devices, each having serial asynchronous input and output channels, can be connected via networks of speed independent arbiter and selector switches. Certain classes of networks have desirable properties: distributed control of routing, conflict resolution, automatic identification of source network address with respect to destination, and exploitation of permissable concurrent operations.

Batch Throughput Efficiency of ADCCP/HDLC/SDLC Selective Reject Protocols

Abstract: The batch throughput efficiency is studied for three variants on selective reject protocols that operate in a full duplex asynchronous response mode and that adhere to the common architectural features of ADCCP, HDLC, and SDLC. In these architectures, the receiver of information frames may use the REJ supervisory frame to request the sender of information frames to back up to an earlier point in the send sequence. Alternatively, the receiver of information frames may issue the SREJ supervisory frame, which requests resending of a single previous information frame followed by continuation of the ongoing send sequence. The first protocol discussed here uses SREJ as the principle method for recovering lost frames but reverts to REJ recovery if certain combinations of errors occur. The second protocol uses SREJ as the only means for recovery. The third protocol uses SREJ for "isolated" frame losses; if a second frame loss occurs within a specified time after the first, then recovery of the first loss is done by REJ. Results plotted for transmission via satellite at 1.544 Mbits/s show that the selective reject protocols permitted by the current versions of ADCCP, HDLC, and SDLC outperform the simpler REJ protocol only for bit error rates in a narrow range. Thus, it may be worthwhile to consider modifications to these architectures that will permit more flexible selective reject protocols.

Universal interface circuit for synchronous and asynchronous buses

Abstract: A universal bus interface circuit can be used in conjunction with either synchronous or asynchronous bus systems. An input terminal is monitored to determine if the bus is synchronous or asynchronous. If the bus is asynchronous, a synchronization circuit generates a synchronous control signal for internal use from an asynchronous select signal. The synchronization circuit also generates an asynchronous hand-shake or acknowledge signal which is applied to the input terminal to indicate completion of the operation. The input terminal is monitored by a host processor.

On the Design of Three-Valued Asynchronous Modules

Abstract: The use of three-valued signals in the design of asynchronous speed-independent modules is considered. The three-valued Post algebra is used as the mathematical basis for multivalued logic design. Asynchronous operation in a three-valued system is defined. Basis data/control signal detectors and control primitives are developed. It is shown that the design of the nonbinary modules only requires the use of standard binary design techniques and the detectors and logic primitives that are developed. A general monitoring and control structure that allows the interconnection of both combinational and sequential modules is described.

N-process synchronization by 4.log2N-valued shared variable

Abstract: The problem of implementing mutual exclusion of N asynchronous parallel processes in a model where the primitive communication mechanism is a test-and-set operation on a shared variable, was the subject of extensive research. While a two-valued variable suffices to insure mutual exclusion, it is shown in [1] that N/2 values are necessary to avoid lockout of any process, and N + 1 values are required to insure bounded waiting time. We introduce the idea of employing randomization in the synchronization protocol and achieve a mutual exclusion, lockout-free, bounded-waiting solution using just 4(log2N+4)-valued shared variable. The protocol is extremely simple, easy to implement, and avoids certain undesirable features present in some of the other solutions.

Asynchronous multi-communication bus sequence

Abstract: An intersystem communication control system in an intersystem link (ISL) unit is provided to accommodate the simultaneous bidirectional transfer of binary coded information between communication busses in a data processing system, wherein the plural communication busses are electrically interconnected by ISL unit twins, and information may be transferred between plural communication busses asynchronously.

Multiplexing Low-Speed Buffered Data Terminals

Abstract: When terminals (data and/or voice), connected to an asynchronous time division multiplexer (ATDM), are buffered and operate at low speed, the arrivals at the multiplexer are correlated. In this paper, we consider the finite buffer behavior of an ATDM with such terminals. An earlier study by Rudin [6] is a special case of this approach. The treatment here is also an improvement over the analysis by Birdsall et al. [1] of an ATDM with speech sources and is suitable for packet voice applications.

Asynchronous multiplex system

Abstract: An asynchronous multiplex system allows full duplex communication between a plurality of terminals each provided with a universal, asynchronous receiver-transmitter (UART) which serially receives data information from a source thereof and is operative to produce a flag signal indicating that all of the bits of a data word have been received for storage therein and are ready for transmission. The multiplex system includes a transmitter section and receiver section servicing a group of data terminals. The transmission section includes a scanner which sequentially interrogates the UARTS associated with each of the corresponding data terminals, and control logic for causing the data words stored in a UART to be delivered to a transmission shift register for temporary storage. The transmitter section further includes an encoder which develops a data code identifying the particular terminal from which the data word is being transmitted. The control logic causes the data word and corresponding code to be simultaneously transmitted as a single, multi-bit data message over a transmission path to the receiving section of another multiplexer servicing another group of terminals. The control logic functions to suspend and scanning process until the transmission shift register is emptied by transmission of the previous data message. The receiving section of each multiplexer includes a pair of shift registers for respectively receiving and storing the data word and data code portions of a data message originating from a terminal in another group thereof, and is provided with control logic for delivering the data word to a terminal identified by the data code.

Method and device for the counting and management of asynchronous events emitted by peripheral devices in a data processing system

Abstract: Method and device for application, counting and management of asynchronous events emanating from peripheral devices connected to a data processing system. This method enables the system to check and regulate the number of events transmitted to the logic for processing by constitution of tables and working queues managed by the firmware. This invention is applicable principally to input-output checkers associated with the computers.

Asynchronous transmission system for binary-coded information

Abstract: ASYNCHRONOUS TRANSMISSION SYSTEM FOR BINARY-CODED INFORMATION ABSTRACT OF THE DISCLOSURE An asynchronous transmission system for binary coded information is disclosed. According to this system, in a transmitting terminal (A), when successive data of the same code in asynchronous data lasts for a predetermined period (T1) of time, a refresh pulse the polarity of which is opposite to the successive data is added to a transmission signal. However, the addition of such a refresh pulse to the transmission signal is inhibited for a predetermined period (T2) of time before a change of data. In a receiving terminal (B), a pulse, the width of which is larger or equal to a minimum period of data, and a pulse, the width of which is smaller or equal to a pulse-width (T0) of a refresh pulse, can be discriminated by a pulse-width discrimination circuit (6). As a result, such a refresh pulse is not present in the output signal of the pulse-width discrimination circuit. Thus, asynchronous data is restored.

An asynchronous garbage collector for the Cambridge File Server

Abstract: This note describes a garbage collector for the Cambridge File Server [Dion80] that runs on a separate machine and which does not require the file server to be disabled during garbage collection. The storage controlled by the file server appears to its clients as a directed graph of files and indices. The file server makes a commitment to maintain a file in existence as long as its unique identifier (UID) is recorded in an index which is accessible from a distinguished root index. Accessibility is defined in an obvious way, one index being accessible from another, which will be called the parent, if its UID is recorded in the parent or in an index accessible from the parent. Since there is no restriction on the recording of UIDs in indices, it is possible as a result of the deletion of index entries to leave detached looped structures which would not be discarded on an ordinary reference count criterion. The file server does maintain reference counts for all objects in it, and deletes an object whose reference count falls to zero. This function is an optimisation within the file server and is for the present purposes not part of garbage collection. The use of an asynchronous garbage collector is justified on the grounds of continuity of service of the file server. To use a separate machine for the purpose requires a few words of explanation. The garbage collection operation requires the construction of potentially substantial data structures, and these could only be made co-resident with the file server's code and data by using an excessively large computer for the file server or by effectively crippling its operation during garbage collection. It is in the spirit of the Cambridge work on distributed computing to use a separate machine for the purpose when it is needed, that machine being available for general use at all other times. Communication between machines is via the Cambridge Ring [Wilkes79]. All interactions consist of a single request packet followed by a single reply packet, as described in the companion paper. Since all transactions are repeatable it is safe simply to retry any operation which fails due to communication errors. The principles of operation of the garbage collector are the same as those of the asynchronous garbage collector developed for a version of the CAP filing system [Birrel178] but two differences in environment affect the 36

Static analysis of the synchronization structure of concurrent programs

Abstract: Software systems which are composed of multiple, asynchronous, communicating processes are increasingly common, often appearing in embedded applications such as avionics systems, life-support systems, and nuclear reactor controllers. Techniques for assisting in ensuring the functional correctness of such systems are few but are clearly needed. The development of one such technique is the subject of this dissertation. In particular, research into the feasibility of developing static analysis techniques is presented. The questions of determining the various ways processes can synchronize, determining what program actions can occur in parallel, and detecting errors in the synchronization structure which result in infinite wait are all explored. Programs written in Ada and Ada-like programming languages are the particular subject of the research, such languages being chosen because of their higher level synchronization mechanisms and potential widespread application. Two major results are presented. The first is a demonstration that, for arbitrary programs, the analysis questions posed above must be considered intractable. The second result is the development of an analysis procedure which, in spite of being exponential in nature, is expected to be able to perform the specified analysis in an acceptably efficient manner for many standard applications. Also presented with the analysis procedure is a programming methodology whose application promotes efficient analysis as well as more understandable concurrent programs. Though the research focusses upon Ada programs the results are at such a level as to be applicable to other concurrent programming languages, such as CSP. In particular the results only depend upon the basic notion of a nondeterministic rendezvous.

Asynchronous interface for keying electronic musical instruments using multiplexed note selection

Abstract: An asynchronous interface includes two memories which store multiplexed keyboard information such that while one memory is writing in newly acquired key information from one musical instrument system at the clock rate of that system, the other memory is reading out previously acquired key information to a second musical instrument system at the clock rate of the second system. Periodically, based on timing signals derived from both systems, the read/write roles of the two memories are reversed. Any number of asynchronously clocked systems, each connected to an associated asynchronous interface, may be keyed by a single key multiplexing device or by the multiplexing information from another asynchronous interface.

A System Overview of Fastbus

Abstract: FASTBUS is an emerging standard for a high-speed data acquisition bus designed to meet the requirements of the next generation of large-scale physics experiments. It incorporates several powerful features: a 32-bit address field; high speed (< 100 nsec) 32-bit data transfers; multiple bus segments permitting a high degree of independent and parallel activity; permits multiple controllers on a single segment; a protocol (uniform system-wide) with asynchronous handshaked operations to reliably accommodate different speed devices, but which also allows synchronous nonhandshaked operations for transferring blocks at maximum speed; the ability to broadcast commands from any point in the system to the whole system or to selected portions of it; and the ability to rapidly extract data from large, sparsely populated arrays. The paper describes these features in more detail and briefly reviews the present state of development of the standard.

An LSI Implementation of an Intelligent CRC Computer and Programmable Character Comparator

Abstract: Manufacturers of MOS microprocessors have been expanding their product families to include function or task oriented LSI peripheral controllers. In the data communications area, circuits such as universal synchronous/asynchronous receiver/transmitters, bit oriented data link controllers, and multiprotocol handlers have greatly simplified systems design. This paper describes a totally unique device-the polynomial generator checker (WC) that monitors transactions on a data bus and performs functions such as programmable character comparisons, parity generation/checking, and "intelligent" block error generation/checking. An overview of character oriented data link controls and cyclic redundancy check/longitudinal redundancy check (CRC/LRC) provides an introduction to the functions and applications of the PGC. Several innovative architectural constructs be described that enable the device to fit within the die cavity of a 16 pin dual-in-like package.

Parallel Execution of a Sequence of tasks on a Asynchronous Multiprocessor.

Abstract: : Given a sequence of tasks to be performed serially, a parallel algorithm is proposed to accelerate the execution of the tasks on an asynchronous multiprocessor by taking advantage of fluctuations in the execution times. A parallel program requiring no critical section is given to implement the algorithm and its correctness is proved. A spacewise more efficient implementation is also given but requires the use of critical sections. An analysis is presented for both implementations to estimate the speed-up achievable with the parallel algorithm. When the execution times are exponentially distributed, and no critical section is used, the algorithm with k processes yields a speed-up of order sq rt of k. (Author)

On the Synthesis Problems of the Semimodular State Chart Theory : I. Distributive Chart

Abstract: We normally classify switching circuits as either synchronous or asynchronous depending on whether or not the signals in the circuit are synchronized with some source of fundamental frequency (or clock) which regulates the entire circuit It is possible to predict the state of a synchronous circuit for any given clock signal if one knows the initial state of the circuit and its logical characteristics However from knowledge of the logical characteristics of the circuit alone, it is impossible in an asynchronous circuit to predict the next state from the present one The state may also depend upon the relative speeds of some of the logical elements which comprise the circuit One of the main objectives of asynchronous theory is to describe the properties of circuits in which their ultimate behavior does not depend on the relative speeds of their elements The semimodular circuit theory introduced by D E Muller and W S Bartkey had the purpose of developing the techniques for designing asynchronous circuits [1, 2, 3] In a series of papers [4, 5, 6], it was reorganized as a theory of H-dimensional space of lattice points In this theory a state of a circuit is specified by a n-tuple z = (zl5, zn), Zje{0, l,,p}, and from a sequence of states z-^-*^->••-, we can construct the sequence of ??-tuples M-»M-* M-»---, such that the i-th component MJ of M=(M\, MJ,, Af*), is a nonnegative integer representing the total number of changes of f-th component of zf-»z->z-» >zj during the state change from z to z For instance, if 2 = (00), z = (01), z = (ll), z = (10),, then M^OO), M = (10),

An LSI Implementation of an Intelligent CRC Computer and Programmable Character Comparator

Abstract: Manufacturers of MOS microprocessors have been expanding their product families to include function or task oriented LSI peripheral controllers. In the data communications area, circuits such as universal synchronous/asynchronous receiver/transmitters, bit oriented data link controllers, and multiprotocol handlers have greatly simplified systems design.

Communication multiplexer having an apparatus for establishing a single line priority

Abstract: A data processing system includes a number of input/output devices coupled to a communication multiplexer by 1 synchronous communication line and a number of asynchronous communication lines. During the polling operation, receive communication lines have high priority and transmit communication lines have low priority. Apparatus in the polling logic gives the synchronous communication line in the receive mode first priority and the synchronous communication line in the transmit mode second priority.

Applications of multiprogramming software to real-time experiments in psychology

Abstract: Multiprogramming operating systems are often advertised as solving the problem of competition among independent tasks operating on the same computer system. In real-time laboratories, multiprogramming systems are much more valuable for their ability to manage the relationships among asynchronous, cooperating tasks that are part of a single experiment. This cooperation allows the programming of paradigms that would otherwise require the use of faster and more expensive hardware. Examples are given from several languages and operating systems, including the small, home-built PSYCLE system and the commercially available VORTEX II system.

Design Rationale for the Interactive Programming Language C S S A for Asynchronous Multiprocessor Systems

Abstract: We give an introduction to major language concepts of CSSA which is illustrated by examples and compared with other languages and models.

Serial Asynchronous Communications between Two Different Nuclear Medicine Computer Systems

Abstract: A serial asynchronous communications interface has been established between a VIP 550 (Ohio Nuclear) and a GAMMA 11 (Digital Equipment Corp.) nuclear medicine computer systems. Data is transmitted either as a variable length ASCII character string (80 bytes) or as a block of 520 bytes (512 bytes of data plus control information and checksum). Data transmission is interlocked; each block of data transmitted from the GAMMA 11 elicits a response from the VIP 550. After initial handshaking, the GAMMA 11, which functions as a remote VIP 550 console, initiates an interaction by transmitting a command to the VIP 550. This command can be either part of the normal VIP repertoire or a command to transmit or receive a 256 × 256 frame of data. VIP format data is sent one line at a time with an acknowledgement after each line. The data is transformed in the GAMMA 11 to GAMMA 11 format. The GAMMA 11 study description block determines the number of frames which must be transmitted or received. Major areas for improvement include increasing the slow transmission rate (9600 baud) and adoption of a standard communications protocol.

The concept of asynchronization

Abstract: Communication between parallel processes may take place in synchronous or asynchronous form. The former has widely been used in various concepts. In contrast, means for asynchronous process relations exist only in a few systems in rudimentary form. In this paper the concept of asynchronization is developed systematically. The underlying data structures as well as operations upon them are defined for various versions.