Showing papers on "Binary number published in 1976"

Efficient generation of the binary reflected gray code and its applications

Abstract: Algorithms are presented to generate the n-bit binary reflected Gray code and codewords of fixed weight in that code. Both algorithms are efficient in that the time required to generate the next element from the current one is constant. Applications to the generation of the combinations of n things taken k at a time, the compositions of integers, and the permutations of a multiset are discussed.

An analysis of the structure and complexity of nonlinear binary sequence generators

Abstract: A method of analysis is presented for the class of binary sequence generators employing linear feedback shift registers with nonlinear feed-forward operations. This class is of special interest because the generators are capable of producing very long "unpredictable" sequences. The period of the sequence is determined by the linear feedback connections, and the portion of the total period needed to predict the remainder is determined by the nonlinear feed-forward operations. The linear feedback shift registers are represented in terms of the roots of their characteristic equations in a finite field, and it is shown that nonlinear operations inject additional roots into the representation. The number of roots required to represent a generator is a measure of its complexity, and is equal to the length (number of stages) of the shortest linear feedback shift register that produces the same sequence. The analysis procedure can be applied to any arbitrary combination of binary shift register generators, and is also applicable to the synthesis of complex generators having desired properties. Although the discussion in this paper is limited to binary sequences, the analysis is easily extended to similar devices that generate sequences with members in any finite field.

A simplified binary arithmetic for the Fermat number transform

Abstract: A binary arithmetic that permits the exact computation of the Fermat number transform (FNT) is described. This technique involves arithmetic in a binary code corresponding to the simplest one of a set of code translations from the normal binary representation of each integer in the ring of integers modulo a Fermat number F t = 2b+ 1, b = 2t. The resulting FNT binary arithmetic operations are of the complexity of 1's complement arithmetic as in the case of a previously proposed technique which corresponds to another one of the set of code translations. The general multiplication of two integers modulo F t required in the computation of FNT convolution is discussed.

A Mathematical Foundation for the Analysis of Cladistic Character Compatibility

Abstract: Using formal algebraic definitions of “cladistic character” and “character compatibility”, the concept of “binary factors of a cladistic character” is formalized and used to describe and justify an algorithm for checking the compatibility of a set of characters. The algorithm lends itself to the selection of maximal compatible subsets when compatibility fails.

Symbol Error Probabilities for M-ary CPFSK: Coherent and Noncoherent Detection

Abstract: Continuous-phase frequency shift keying (CPFSK) is discussed and theoretical predictions for symbol error probabilities are derived, where the memory inherent in the phase continuity is used to improve performance. Previously known results concluded that binary CPFSK can outperform coherently detected PSK at high SNR. New results presented here show that M -ary CPFSK outperforms more tranditionally used M -ary modulation systems. Specifically, coherently detected quaternary CPFSK with a five-symbol interval decision can outperform coherent QPSK by 3.5 dB, and octal coherent CPFSK with a three- symbol decision can outperform octal orthogonal signaling by 2.6 dB at high SNR. Results for coherently detected and noncoherently detected CPFSK are derived. These performance improvements are estimates derived from symbol error probability upper bounds. Monte Carlo simulation was performed which then verified the results.

A fast division technique for constant divisors

Abstract: A fast algorithm for division by constant divisors is presented. The method has proved very useful implemented as microcode on a binary machine, and can be adapted directly into hardware. The mathematical foundations of the algorithm are presented as well as some performance measures.

Fault tolerant least recently used algorithm logic

Abstract: Binary logic is added to the binary logic normally utilized for the purpose of generating and decoding binary code combinations which reflect the order of use of a number of units, utilized in sequence, to thereby indicate the unit least recently used (LRU). Disclosed is the utilization of six binary bits which are updated in accordance with a sequence of use of four units to thereby indicate the least recently used one of the four units. In accordance with known LRU techniques, there are 24 valid binary bit combinations that reflect the sequence of use of the four units. The provision of 6 binary bits in the LRU code are capable of assuming 64 different permutations, therefore 40 combinations of binary bits are considered invalid when utilizing the LRU code. The present invention utilizes certain of the invalid binary bit combinations to identify units that have been removed from further use because of a fault condition, and which code continues to identify the sequence of use of those units which have not been eliminated from further use. The code chosen to identify a faulty unit and the sequence of use of the remaining units is fault tolerant in that additional errors in the coding mechanism can be tolerated, and ignored, while maintaining the ability to identify faulty units and sequence of use of the remaining units.

Associated Complex Formation in a Binary Solution and the Concentration Fluctuation: The Chloroform–Diethyl Ether System

Abstract: The relations between the associated complex formation and the concentration fluctuation in a binary solution were derived. The concentration fluctuation of a chloroform–diethyl ether system was determined by observing light-scattering spectra at various concentrations. The theoretical values of the concentration fluctuation of this system were calculated from the proposed relation by the use of the shape and the number population of the associated complex, as determined from the infrared absorption intensity measurements. The observed and calculated concentration fluctuations agreed quite well.

The Effect of Single Bit Errors in Standard Nonlinear PCM Systems

Abstract: The effects of independent bit errors are calculated for nonlinear PCM systems. General simplified computer formulas are given for natural binary and binary folded PCM codes. Analytical formulas are produced for μ-quantization, binary folded PCM, and speech-like input signal density functions.

Data transmission system for transmitting primary and secondary intelligence

Abstract: Data transmission in, for instance, a PCM system, is effected by translation of the binary codes into ternary combinations such that to each binary code there is provided n ternary codes with the choice of the ternary code sent being dependent on secondary intelligence, such as signalling information and/or synchronization information, to be sent. In the example described a binary bit stream is split into three bit blocks each of which is converted into a three bit ternary code.

Autocorrelation function factor generating method and circuitry therefor

Abstract: For a delta modulated signal wave comprising a digital carrier wave modulated by an analog wave and represented accordingly as a bivalued digital data bit stream, a correlation function factor is generated by delaying the bit stream in time by an integral multiple of bits and accumulating the successive individual products over a predetermined number of bits of successive individual bits delayed in time and the corresponding currently appearing bits. The circuitry is extremely simple; readily procurable components only are required. A dual input exclusive OR (XOR) gating circuit is connected to the source of delta modulated signal bit stream and to an N-bit digital binary shift register also connected to the source. A stream of successive bivalued products of the current bits and the time delayed bits over a period of N-bits is obtained from the XOR gating circuit and applied to a bidirectional digital counting circuit from which an autocorrelation function factor is delivered.

Modular binary half-adder

Abstract: Half-adder logic modules employing separate summing and carry circuitry are used in the construction of a modular binary half-adder. Carry bits of less significant digits are calculated independent of and prior to the calculation of corresponding sum bits, thus allowing rapid propagation of such carry bits to more significant digits and subsequent parallel summation of the sum bits using the carry bits previously calculated.

Propagation line adder and method for binary addition

Abstract: A propagation line adder may be fabricated by replicating a unit circuit along a sense and reference propagation path. Each unit circuit corresponds to bits of the same order of magnitude of the binary addends. Selected segments of the sense propagation path are set a specified logical potential value and are coupled according to control signals generated within the unit circuit in response to the addend bits. The reference propagation path is then discharged and a sense amplifier, coupled to each segment of the reference and sense propagation paths, detects the state on corresponding segment of the sense propagation path. The propagation line adder implements an algorithm which produces the binary sum of two numbers by complementing the exclusive-or function of the addends according to a shifted product function. The shifted product function includes a carry in bit as its lowest order bit.

An analysis of universal logic modules

Abstract: This note considers the algebraic synthesis of universal logic modules (ULMs) which can realize any given function f(x) of n input binary input variables. It is shown that classic canonic expansions confirm the topology of all known ULM circuit configurations.

Multi-valued multi-threshold networks

Abstract: In this paper we propose multi-valued multi-threshold networks (MVTN's) to realize multi-valued logic functions. A definition, transformations of multi-valued functions and network syntheses for an MVTN are described. There are three emphases on the MVTN's: 1) any arbitrary multi-valued logic function can be realized by an MVTN, 2) an MVTN can be composed of conventional threshold elements, and 3) various synthesis procedures for binary multi-threshold networks can be applied to MVTN's.

Natural binary to logarithmic binary conversion device with means for range selection

Abstract: In practice it is often desirable to represent only a given, selectable dynamic range of a measuring signal, preferably in logarithmic form. This is achieved in accordance with the invention in that from the measured value in the form of a binary number only the positions corresponding to the desired dynamic range are selected for forming the base number, the weight of the most significant bits having the value "1" being converted into a binary number. The mantissa is derived from the following positions, i.e. independent of the selected dynamic range, so that even when the most significant bit is in the last position, a mantissa comprising the full number of positions is formed. The magnitude of the dynamic range is chosen by omitting the correspondingly more significant positions of the base number formed for the maximum range. The position of the dynamic range can be shifted in that the inputs of the circuits for forming the base number and the mantissa are shifted with respect to the lines supplying the individual positions of the measured value.

On the numerical evaluation of theJ-integrals

Abstract: This is a third paper dealing with the numerical evaluation of the light changes exhibited by close binary systems; for previous communications, Lanzano, 1976a, b.

Image analysis system and method for minimizing paralysis angle

Abstract: A system and method of counting and analyzing each image of a plurality of features by minimizing the paralysis angle associated with each feature whose image is being analyzed by line-to-line scanning techniques is disclosed. The system and method involves the temporary storage of the X-coordinates of the boundary intercepts of each feature along one line scan and then selecting the last-to-occur of such intercepts to generate in memory a modified binary video signal to define the trailing edge of the feature. The modified video signal is stored one line scan and compared with the next real time line scan video signal in a manner such that the trailing edge data very accurately represents the actual position of the trailing edge of the feature.

Integer and floating point to binary converter

Abstract: In a data processing system having a plurality of storage units, each unit therein storing in integer or normalized floating point format, an exponent sign bit, an exponent field, an integer/fraction sign bit, and an integer/fraction field, a converter transforms the stored data into pure binary values of selectively the same or the inverse relative order. To convert into the same relative order, the exponent sign bit is complemented if the integer/fraction sign bit is a logical zero and the exponent is complemented if otherwise. Thereafter, the integer/fraction bit is complemented. To convert into the inverse relative order, the exponent sign bit is complemented if the integer/fraction sign bit is a logical one and the exponent field is complemented if otherwise. Also, the integer/fraction field is complemented.

Method for the transmission of binary information by means of a frequency-modulated signal and a circuit for performing that method

Abstract: A transmission of a binary signal which transmission is immune to interference is obtained by transmitting the bits of the binary signal by means of a frequency-modulated signal in which a cycles of a first frequency f 1 are followed by b cycles of a second frequency f 2 for a binary zero value and b cycles of the first frequency f 1 are followed by a cycles of the second frequency f 2 for a binary one value.

Binary logarithms for computing integral and non-integral roots and powers

Abstract: This paper suggests a method of utilizing binary logarithms to compute the power, root, or any exponential of a number It is an extension of Mitchell's (1962) technique Due to the approximation of the binary logarithms, there will be errors in the calculations of the results However, using this method, no logarithmic tables are required Approximations to binary logarithms are very easy to generate by simple shifting and counting Evaluating power, roots, and any exponent of a number is reduced to simple addition and subtraction operations Finally the approximation error might be reduced hy adding a fixed number to correct the binary logarithms

Fractional binary to decimal converter

Abstract: The present invention relates to a simplified apparatus for converting a ary fraction input into a Natural Binary Coded Decimal (8421 code) and subsequently into a decimal output with the proper sign. The invention provides means for selectively shifting and summing the binary fraction to effect a multiplication by ten. An integer portion to the left of a fixed binal point and a remaining fraction portion to the right are produced. The integer portion is extracted as a BCD character which is converted via a nixie display into decimal form. Shifting and summing successive remaining fractions and displaying successive integer portions produces a final decimal number which corresponds to the binary fraction input.

Optical Gray to binary code converter

Abstract: Signals representative of information bits are converted from one binary code, for example, Gray code, to another binary code, for example, conventional binary, and vice versa, by advantageously employing optical couplers in conjunction with buffer amplifiers. The optical couplers include light emitting diodes and associated phototransistors which are uniquely connected in circuit relationship with the outputs of the buffer amplifiers to effect the desired code conversions.