Showing papers on "Cascade amplifier published in 2017"

Multipath recycling method for transconductance enhancement of folded cascade amplifier

Abstract: A multipath recycling method to enhance transconductance of the folded cascode amplifier is presented in this paper. The proposed method utilizes two idle paths to conduct small signal current, which leads to significant enhancement of transconductance compared to conventional folded cascade structure. Moreover, the improved performance is almost at no expense of power dissipation. The proposed multipath recycling and the conventional amplifiers are all designed in UMC 0.18 μm CMOS technology. Simulation results demonstrate that the transconductance of the proposed amplifier is improved by 450% and dc gain enhances 16 dB when compared with the folded cascode counterpart.

Optical receiver module

Abstract: An optical receiver module including: two amplifier arrays in each of which transimpedance amplifiers and first capacitors are arranged in an alternating manner, and an optical detector array, located between the two amplifier arrays, in which a plurality of optical detectors are aligned, wherein the plurality of optical detectors are coupled in an alternating manner to one of the transimpedance amplifiers of one of the two amplifier arrays and to one of the transimpedance amplifiers of the other of the two amplifier arrays, and for each specified optical detector of the plurality of optical detectors, the specified optical detector is coupled to one of the first capacitors of a second amplifier array of the two amplifier arrays, the second amplifier array being different from a first amplifier array that includes one of the transimpedance amplifiers to which the specified optical detector is coupled.

Gain-boosted dynamic amplifier for pipelined-SAR ADCs

Abstract: A high-gain and high-speed gain-boosted dynamic amplifier for pipelined-successive approximation register ADCs is presented. A cross-coupling cascode topology is proposed to boost the gain of a single-stage dynamic amplifier. The proposed dynamic amplifier achieves a voltage gain of 32 under a 1.2 V power supply in 130 nm CMOS technology. Sampling at 150 MS/s, the proposed dynamic amplifier consumes a total power of 0.22 mW.

A New Instrumentation Amplifier Architecture Based on Differential Difference Amplifier for Biological Signal Processing

Abstract: In this paper, a new Instrumentation Amplifier (IA) architecture for biological signal pro-cessing is proposed. First stage of the proposed IA architecture consists of fully balance differential difference amplifier and three resistors. Its second stage was designed by using differential difference amplifier and two resistors. The second stage has smaller number of resistors than that of conventional one. The IA architectures are simulated and compared by using 1P 2M 0:6-m CMOS process. From HSPICE simulation result, lower common-mode voltage can be achieved by the proposed IA architecture. Average common-mode gain (Ac) of the proposed IA architecture is 31:26 dB lower than that of conventional one under 3% resistor mismatches condition. Therefore, the Ac of the proposed IA architecture is more insensitive to resistor mismatches and suitable for biological signal processing.

High-Gain Low Noise Figure Complementary Metal Oxide Semiconductor Amplifier with Low Current Consumption

Abstract: A radio frequency low noise amplifier circuit with a receive signal input, a receive signal output, and a voltage source include a low noise amplifier and a coupled inductor circuit with a primary inductive chain connected to the output of the low noise amplifier and to the voltage source. The coupled inductor circuit further includes a secondary inductive chain with a first inductor electromagnetically coupled to the primary inductive chain, and a second inductor in series with the first inductor and magnetically coupled to the primary inductive chain. The second inductor is connected to a feedback node of the low noise amplifier. There is an output matching network connected to the first inductor of the secondary inductive chain and to the receive signal output.

A Highly Linear and Efficient CMOS Power Amplifier With Cascode–Cascade Configuration

Abstract: This letter proposes a highly efficient CMOS linear power amplifier (PA) with cascode–cascade configuration The proposed configuration improves AM–PM distortion through a capacitance variation compensation of the input capacitance of a common-gate stage in the main amplifier and a common-source stage of an auxiliary amplifier In addition, the current consumption in the low-power region is significantly reduced structurally because the auxiliary amplifier is turned off The PA is implemented in 018- $\mu \text{m}$ CMOS process with an output combining network in printed circuit board It provides an average power of 245 dBm with a PAE of 456% for a long-term-evolution 10-MHz up-link signal with the ACLRE–UTRA of −30 dBc at 2 GHz

Low voltage and low power UWB CMOS LNA using current-reused and forward body biasing techniques

Abstract: A ultra-wideband (UWB) low noise amplifier (LNA) was designed and fabricated in 0.18μm CMOS technology. The successful integration of current-reused and forward body biasing (FBB) techniques in a cascade amplifier can enable an aggressive scaling of the supply voltages, V dd and Vg1 to 1.0V and 0.53V The low voltage feature from FBB leads to more than 50% saving of power dissipation to 5.2mW. The measured power gain (S21) can reach 10.55∼12.6dB and noise figure (NF50) is 3.2∼3.95 dB through the UWB (3∼10.5GHz). This UWB LNA with small chip area (0.69mm2) provides a solution of low voltages, low power, and low cost.

A 2.4-GHz CMOS Common-Gate Combining Power Amplifier With Load Impedance Adaptor

Abstract: A CMOS common-gate (CG) combining power amplifier is introduced, which has a simple load impedance adaptor. The CG stage of a cascode amplifier consists of a main amplifier with a load impedance adapter and an auxiliary amplifier with a phase compensator, which are biased for classes AB and C, respectively. The proposed configuration not only increases the efficiency of the power amplifier (PA) at back-off powers, but also increases the linearity at high output powers by canceling AM–AM and AM–PM nonlinearities of the main amplifier with those of the auxiliary amplifier. A load impedance adaptor can be used to match two different optimum load impedances of the main and auxiliary amplifiers simultaneously. A phase compensator is introduced to match the output phases of both amplifiers. It has a die size of $0.9 \times 1.63$ mm2 operates at 2.484 GHz with a 3.3 V supply, which is implemented with the 0.18- $\mu \text{m}$ CMOS technology. It shows a linear output power of 22.1 dBm with a PAE of 32% for an 802.11 n signal at error vector magnitude (EVMs) of −25 dB, and it also shows apparent efficiency improvements at back-off powers.

A Low-Noise, Low-Power, Wide Dynamic Range Logarithmic Amplifier for Biomedical Applications

Abstract: This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18μm CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027mm2. The overall circuit consumes 9.75μW from a single 1.5V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80dB input dynamic range (from 10μV to 100mV), a bandwidth of 4Hz–10kHz, and a total input-referred noise of 5.52μV.

Power amplifier, radio remote unit, and base station

Abstract: A power amplifier, a radio remote unit (RRU), and a base station, where the power amplifier includes an envelope controller, a main power amplifier, and an auxiliary power amplifier. The main power amplifier and the auxiliary power amplifier both set an envelope voltage output by the envelope modulator as operating voltages, and because the operating voltages of the main power amplifier and the auxiliary power amplifier may be adjusted simultaneously, symmetry of the power amplifier is improved, and an efficiency loss occurring probability is low, thereby enhancing efficiency of the power amplifier.

A High Bandwidth (DC-40 GHz) Pseudo Differential Distributed Amplifier in 0.18-μm RF CMOS

Abstract: This study presents a CMOS distributed amplifier (DA) with pseudo differential amplifying that achieves DC-40GHz bandwidth (BW) in 0.18-μm RF CMOS process. The DA with three-stage amplifying cells was proposed to improve the DA performance. The inter-stage was composed of pseudo differential amplifying for bandwidth extension. By incorporating the pseudo differential amplifier configuration and capacitor-less circuit in the stages, the DA provides average gain and high bandwidth. The simulation results showed that the DA has a S21 of 6.4dB, 3-dB BW from DC up to 40GHz. It also has a minimum noise figure (NF) of 4.27dB, one dB compression point (P1dB) of +3.5dBm, a high reverse isolation S12 of less than −15dB, an input return loss S11 and output return loss S22 of less than −16 and −12dB, respectively. It consumes 115mW and occupies a total active area of 0.27mm2.

A Low-Noise Charge Amplifier for the ELENA Trajectory, Orbit, and Intensity Measurement System

Abstract: A low-noise head amplifier has been developed for the extra low energy antiproton ring beam trajectory, orbit, and intensity measurement system at CERN. This system is based on 24 double-electrode electrostatic beam position monitors installed around the ring. A head amplifier is placed close to each beam position monitor to amplify the electrode signals and generate a difference and a sum signal. These signals are sent to the digital acquisition system, about 50 m away from the ring, where they are digitized and further processed. The beam position can be measured by dividing the difference signal by the sum signal while the sum signal gives information relative to the beam intensity. The head amplifier consists of two discrete charge preamplifiers with junction field effect transistor (JFET) inputs, a sum and a difference stage, and two cable drivers. Special attention has been paid to the amplifier printed circuit board design to minimize the parasitic capacitances and inductances at the charge amplifier stages to meet the gain and noise requirements. The measurements carried out on the head amplifier showed a gain of 40.5 and 46.5 dB for the sum and difference outputs with a bandwidth from 200 Hz to 75 MHz and an input voltage noise density lower than $400~\text {pV}/\surd \text{Hz}$ . Twenty head amplifiers have been already installed in the ring and they have been used to detect the first beam signals during the first commissioning stage in November 2016.

A multi-path ring amplifier with dynamic biasing

Abstract: This paper presents a new method for ring amplifier biasing to improve their stability while maintaining high slew rate. A multi-path ring amplifier is proposed for switched capacitor applications that allows accurate charge transfer at high speeds. Dynamic biasing improves large signal slewing without affecting residue amplifier settling performance. Stable operation is possible because the auxiliary path turns off dynamically, allowing the main path to be optimized for accuracy. The proposed multi-path amplifier was used in the first stage of a pipelined ADC in 180nm CMOS. Measurements show SNDR, SNR, and SFDR of 73.6 dB, 74.6 dB and 85.5 dB respectively, sampled at 10 MS/s, and consumes 7.68 mW.

Low power UWB CMOS LNA using resistive feedback and current-reused techniques under forward body bias

Abstract: A ultra-wideband (UWB) low noise amplifier (LNA) has been realized in 0.18μm CMOS technology. The current-reused method combined with forward body bias (FBB) in a cascade amplifier can enable an aggressive voltages scaling, such as V DD and V G1 to 1.0V and 0.53V, i.e. 44.5% and 70.6% reduction compared to the typical V DD of 1.8V. The low voltage feature from FBB leads to more than 50% saving of power dissipation to 5.2mW. The on-chip measurement indicates power gain (S21) of 10.55∼12.6dB and noise figure (NF50) of 3.2∼3.95 dB through the UWB (3∼10.5GHz). This UWB LNA with small chip area (0.69mm2) provides a solution for low voltages, low power, and low cost.

A wideband noise-cancelling CG-CS LNA with transformer source coupling

Abstract: A wideband noise-cancelling low noise amplifier is implemented in 0.13-μm CMOS technology. The amplifier is composed of a common gate amplifier and a common source amplifier working as a BALUN and a noise cancelling stage. A 11:1 transformer is located at sources of the amplifier. The transformer works as source degeneration for low noise in the common source amplifier and increases Vgs at the common source amplifier to improve gain. Therefore, low gain by source degeneration is compensated by increased Vgs. Simulated performance shows 11 dB of gain and 3.2 dB of noise figure at 1 to 4 GHz.

High-power all-optical-fiber cascade amplifier

Abstract: The invention relates to a high-power all-optical-fiber cascade amplifier, which comprises a seed source (1), an amplification stage (2) and an output terminal (3), wherein an output end of the seed source (1) is connected with an output end of the amplification stage (2), and an output end of the amplification stage (2) is connected with the output terminal (3). The invention provides a technical scheme with high operability for high-power and high-brightness laser output. Provided by the invention is a high-power cascade amplification system which has a high power output capacity and also has brightness maintenance; a simple MOPA structure is adopted, myriawatt high-brightness laser output can be achieved by only primary amplification; the amplification stage adopts a double-end pump structure, so that the heat dissipation difficulty is reduced; and commercial production is easy to realize.

Investigation of direct-coupled amplifier topologies for wireless communication systems using normally-on mHEMT technology

Abstract: This paper presents direct-coupled DC-50 GHz two-stage baseband amplifier topologies realized in a 35 nm gate-length InAlAs/InGaAs mHEMT technology. These are key components of future single-chip receiver MMICs for point-to-point communication systems. Three interstage coupling approaches are investigated: resistive coupling, a diode-level-shifter and a Kukielka amplifier. The Kukielka amplifier features the best performance in terms of gain-bandwidth-product and represents the state of the art for this topology. The investigated two-stage amplifier circuits achieve up to 21 dB gain and a 3 dB bandwidth of 53 GHz, requiring less than 300×300 μm2 chip area. The presented level-shifter circuit has a 3 dB bandwidth of up to 150 GHz and an insertion loss of less than 3.5 dB.

A compensation technique for recycling folded-cascode amplifier

Abstract: A compensation technique for recycling folded cascade (RFC) amplifier is presented. By applying the compensation technique, the proposed modified recycling folded cascade (MRFC) circuit achieves better slew rate and unity-gain frequency compared with RFC amplifier. The proposed circuit is designed using TSMC 0.18µm CMOS technology. The amplifier is verified with a 5.6pF output load under 1.8V power supply. When compared to the RFC amplifier, the proposed amplifier achieves 80MHz increment in unity-gain frequency (134.2MHz versus 214.3MHz), 13.4V/µs increment in slew rate (94.1V/µs versus 107.5 V/µs), and 19.6dB increment in dc gain (73.2dB versus 53.6dB). The power consumption of the amplifier is 870µW at a 1.8V supply.

Feed reflected Doherty amplifier and method for driving Doherty amplifiers

Abstract: The feed reflected Doherty amplifier utilizes the output characteristics of the carrier amplifier to control the input signal of the peaking amplifier to improve the gain, linearity and efficiency of a Doherty amplifier. The feed reflected Doherty amplifier comprises an input power splitter, a carrier amplifier branch and a peaking amplifier branch combined into a common load, an output directional coupler and an input directional coupler connected via a phase shift element.

Cascode switch for amplifier

Abstract: Aspects of this disclosure relate to a cascode circuit electrically coupled between an amplifier configured to amplify a radio frequency (RF) signal and different loads. The cascode circuit can function as a switch to selectively provide an output from the amplifier to a number of different loads. In certain embodiments, the cascode circuit can be electrically coupled between different stages of a multi-stage power amplifier. For instance, the amplifier can be a first stage of the multi-stage power amplifier and the different loads can include different power amplifier transistors of a second stage of the multi-stage amplifier. The cascode circuit can be implemented by bipolar transistors according to certain embodiments.

Self-biasing output booster amplifier and use thereof

Abstract: A self-biasing output booster amplifier having an input amplifier stage, an output amplifier stage being operatively connected to an output of the input amplifier stage, and first and second current copying circuits. The second current copying circuit is biased from an output of the self-biasing output booster amplifier. The first and second current copying circuits are configured to copy at least a portion of the current through the output amplifier stage. The sum of the output of the second current copying circuit and the output of the output amplifier stage provides the output current of the self-biasing output booster amplifier, Finally, the input amplifier stage is biased from the output of the second current copying.

A 0.02% THD and 80 dB PSRR filterless class D amplifier with direct lithium battery hookup in mobile application

Abstract: This paper presents a fully integrated CMOS filterless class D amplifier that can directly hook up lithium battery in mobile application The proposed amplifier embodies a 2-order feedback path architecture instead of direct feedback of output to input of the integrator to decrease the high frequency intermodulation distortion associated with direct feedback and eliminate the integrator input common mode disturbance from the output in ternary modulation. The prototype class D amplifier realized in 0.35 μ m digital technology achieves a THD+N of 0.02% when delivering 400 mW to an 8Ω load from V DD =3.6 V. The PSRR of the prototype class D amplifier is 80 dB at 217 Hz. Furthermore a filterless method that can eliminate the external LC filter is employed which offers great advantages of saving PCB space and lowering system cost. In addition the prototype class D amplifier can operate in large voltage range with V DD range from 2.5 to 4.2 V in mobile application. The total area of the amplifier is 1.7 mm 2 .

Design of two-stage fully-integrated CMOS power amplifier for K-band applications

Abstract: This paper presents a K-band power amplifier integrated circuit using Samsung 65 nm CMOS process. The power amplifier adopts two-stage configuration for high power gain. The input, output, and inter-stage transformers are integrated. By neutralizing gate-drain capacitance using cross-coupled capacitors, the power gain and stability were improved. Its chip size is 0.78 × 0.62 mm2. The implemented two-stage power amplifier showed a power gain of 19.6 dB, a saturated output power of 13.5 dBm, and an efficiency of 7.19 % with a supply voltage of 1.1 V at the frequency band of 24 GHz.

Low Power SI Class E Power Amplifier and RF Switch For Health Care

Abstract: This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software. And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate goal for such application is to reach high performance and low cost, and between high performance and low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can transmit 16dBm output power to a 50{\Omega} load. The performance of the power amplifier and switch meet the specification requirements of the desired.

Variable gain amplifier and driver implementing the same

Abstract: A driver that drives an optical device, such as laser diode (LD) and/or optical modulator, is disclosed. The driver includes a variable gain amplifier (VGA) and a post amplifier. The post amplifier amplifies an output of the VGA to a preset amplifier as varying the gain of the VGA. The VGA includes two differential pairs each amplify the input signal oppositely in phases thereof and outputs of the differential pairs are compositely provided to the post amplifier. The gain of the VGA is varied by adjusting contribution of the second differential pair to the output of the VGA.

Push-pull totem-pole RF power amplifier with reactive matching networks

Abstract: Push-pull RF power amplifiers (PA) are generally composed of two single ended amplifiers operating in anti-phase. Transformers or baluns are used to split the input signal for the amplifiers, and combine their outputs. An alternative approach described here, is the asymmetric totem-pole amplifier which consists of two N-channel FETs stacked one on top of each other, with the output taken from their common node. The upper device operates as a sourcefollower to supply current to a load, and the lower as a common-source amplifier to sink current. A reactive inductorcapacitor matching network matches the high input impedance of the source-follower to 50 Ω. Under simulation, a 680 MHz prototype achieved 69.5% drain efficiency at a 25.1 dBm 1 dB compression point (P1dB). Simulated waveforms verified that the two paths of the PA operated in anti-phase. A practical PA achieved a 23.5 dBm P1dB at 48.1% drain efficiency. The measured second harmonic distortion (HD2) was suppressed by -47 dBc relative to the fundamental as is typical of a push-pull PA.

Noise cancellation in amplifier systems

Abstract: A low power amplifier architecture that employs a single-ended (single triode) push-pull (SEPP) vacuum tube and output transformer arrangement, and that cancels unwanted amplifier signal components such as hum and noise. The SEPP amplifier operates to cancel power supply ripple and local EMI induced noise in the output transformer by providing reverse polarity of the primary coils of the output transformer.

Method for Outputting Charging Current and Power Amplifier

Abstract: A method for outputting a charging current is provided. When a power amplifier is connected to a device, the power amplifier acquires recognition information from the device. The power amplifier determines the type of the device according to the foregoing recognition information, and selects, according to the type of the device, a current to output. The power amplifier outputs the selected current to the device, in which the current is used to charge the device.