Showing papers on "Chip published in 2002"

Three dimensional IC package module

Abstract: In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to chip vias are created by etching and filling a hole from the back of a chip through the silicon substrate stopping at the first level of metalization and invoking the wiring of the chip to complete the path to the top side. The chip in the stack are aligned so that chip to chip vias form columns. Signal and power can travel the full length of a column from the bottom chip to the chip on top, or the wiring within the chips can interrupt the signal flow and form interstitial connections. Interstitial connections can also be used to enhance the wireability between chips in the stack. To accommodate cooling the chips in the stack are made in varying sizes and are ordered in size from the largest at the bottom of the stack to the smallest at the top of the stack. This provides a stair case like structure to allow heat sinks to be attached to each step formed by a chip and the smaller chip above. An interface substrate sits at the bottom of the stack and provides for communication external to the stack by connecting the columns of chip to chip vias to an array of pins to mate with a connector. The short distances that signals must travel lends this three dimensional stacked chip package to high performance for off chip communications.

Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof

Abstract: A three-dimensional, multi-chip package with chip selection pads formed at the chip-level and a manufacturing method thereof are provided. The three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, (N−1) chip selection pads, an insulation layer, (N−1) metal wirings, upper connection terminals, lower connection terminals, and trench wirings. The chip selection terminal of each chip is separated from the chip selection of the other chips by the chip selection pads formed at the chip-level.

Chain: a delay-insensitive chip area interconnect

Abstract: The increasing complexity of system-on-a-chip designs exposes the limits imposed by the standard synchronous bus. The authors propose a mixed system as a solution.

An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes

Abstract: This paper introduces an accurate method of modeling the performance of high-speed chip-to-chip signaling systems. Implemented in a simulation tool, it precisely accounts for intersymbol interference, cross-talk and echos as well as circuit related effects such as thermal noise, power supply noise and receiver jitter. We correlated the simulation tool to actual measurements of a high-speed signaling system and then used this tool to make tradeoffs between different methods of chip-to-chip signaling with and without equalization.

High-frequency chip packages

Abstract: A packaged semiconductor chip includes features such as a chip carrier having a large thermal conductor which can be solder-bonded to a circuit board so as to provide enhanced thermal conductivity to the circuit board and electromagnetic shielding and a conductive enclosure which partially or completely surrounds the packaged chip to provide additional heat dissipation and shielding. The packaged unit may include both an active semiconductor chip and a passive element, desirably in the form of a chip, which includes resistors and capacitors. Inductors may be provided in whole or in part on the chip carrier. A module includes two circuits and an enclosure with a medial wall between the circuits to provide electromagnetic shielding between the circuits.

Channel-independent synchronization of orthogonal frequency division multiple access systems

Abstract: We develop synchronization algorithms for both the downlink and the uplink of quasi-synchronous and asynchronous orthogonal frequency division multiple access systems. Unlike existing alternatives, the proposed time- and carrier-offset estimators do not require the transmission of known sequences and exhibit performance independent of the underlying channel zero locations. The only necessary assumption is that there are virtual subcarriers which are not occupied by any user. We derive a closed-form variance expression for the carrier-offset estimator at high signal-to-noise ratio (SNR), as a function of the number of active users and the SNR. We compare our method with alternative ones and validate our theoretical derivations with simulation results.

Prediction of tool and chip temperature in continuous and interrupted machining

Abstract: In this paper, a numerical model based on the finite difference method is presented to predict tool and chip temperature fields in continuous machining and time varying milling processes. Continuous or steady state machining operations like orthogonal cutting are studied by modeling the heat transfer between the tool and chip at the tool—rake face contact zone. The shear energy created in the primary zone, the friction energy produced at the rake face—chip contact zone and the heat balance between the moving chip and stationary tool are considered. The temperature distribution is solved using the finite difference method. Later, the model is extended to milling where the cutting is interrupted and the chip thickness varies with time. The time varying chip is digitized into small elements with differential cutter rotation angles which are defined by the product of spindle speed and discrete time intervals. The temperature field in each differential element is modeled as a first-order dynamic system, whose time constant is identified based on the thermal properties of the tool and work material, and the initial temperature at the previous chip segment. The transient temperature variation is evaluated by recursively solving the first order heat transfer problem at successive chip elements. The proposed model combines the steady-state temperature prediction in continuous machining with transient temperature evaluation in interrupted cutting operations where the chip and the process change in a discontinuous manner. The mathematical models and simulation results are in satisfactory agreement with experimental temperature measurements reported in the literature.

Chip-interleaved block-spread code division multiple access

Abstract: A novel multiuser-interference (MUI)-free code division multiple access (CDMA) transceiver for frequency-selective multipath channels is developed. Relying on chip-interleaving and zero padded transmissions, orthogonality among different users' spreading codes is maintained at the receiver even after frequency-selective propagation. As a result, deterministic multiuser separation with low-complexity code-matched filtering becomes possible without loss of maximum likelihood optimality. In addition to MUI-free reception, the proposed system guarantees channel-irrespective symbol detection and achieves high bandwidth efficiency by increasing the symbol block size. Filling the zero-gaps with known symbols allows for perfectly constant modulus transmissions. Important variants of the proposed transceivers are derived to include cyclic prefixed transmissions and various redundant or nonredundant precoding alternatives. (Semi-) blind channel estimation algorithms are also discussed. Simulation results demonstrate improved performance of the proposed system relative to competing alternatives.

Mitigating multiple access interference and intersymbol interference in uncoded CDMA systems with chip-level interleaving

Abstract: The presence of intersymbol interference (ISI), in addition to multiple access interference, severely hampers the performance of a code-division multiple-access (CDMA) communication system. In such a situation, channel coding can be used to obtain better performance, but at the cost of a reduction in rate of flow of information. In this paper, it is shown with the help of simulation results that the chip-interleaved CDMA system effectively combats ISI without requiring additional channel coding. The system differs from the conventional CDMA system in the sense that, the chip sequence resulting from the pseudo noise (PN) sequence modulation is interleaved before transmission. Two receivers are proposed, one based on the turbo equalization method which employs a maximum a posteriori equalizer of exponential complexity and the other based on minimum-mean square error-optimized iterative interference cancellation principles which is of linear complexity. Simulation results are provided which show that error rates close to the no-ISI single-user case can be obtained. The shortcomings of the coded CDMA with turbo detection system in the presence of ISI are also discussed.

High-frequency digital controller IC for DC/DC converters

Abstract: This paper describes a complete digital controller IC for high-frequency switching converters. Novel architecture and configurations of the key building blocks: A/D converter, compensator and digital pulse-width modulator, are introduced to meet the requirements of tight output voltage regulation, highspeed dynamic response, and programmability without external passive components. The implementation techniques are experimentally verified on a prototype chip that takes less than 1 mm/sup 2/ of silicon area in a standard 0.5 /spl mu/ digital CMOS process and operates at the switching frequency of 1 MHz.

Method of forming IC package having upward-facing chip cavity

Abstract: A method of forming an integrated circuit package with an upward-facing chip cavity such that the fabrication of the substrate and the packaging of silicon chip are combined. By forming a patterned dielectric layer to expose bonding pads on a silicon chip and subsequently connecting the bonding pad on the chip with trace lines on the substrate through electroplating, reliable connections between the chip and substrate are formed and no more bubbles are formed inside the dielectric layer.

Transmitter photonic integrated circuits (txpic) and optical transport networks employing txpics

Abstract: A photonic integrated circuit (PIC) chip comprising an array of modulated sources, each providing a modulated signal output at a channel wavelength different from the channel wavelength of other modulated sources and a wavelength selective combiner having an input optically coupled to received all the signal outputs from the modulated sources and provide a combined output signal on an output waveguide from the chip. The modulated sources, combiner and output waveguide are all integrated on the same chip.

Transmitter photonic integrated circuit (TxPIC) chip architectures and drive systems and wavelength stabilization for TxPICs

Abstract: A monolithic transmitter photonic integrated circuit (TxPIC) chip comprises an array of modulated sources formed on the PIC chip and having different operating wavelengths according to a standardized wavelength grid and providing signal outputs of different wavelengths. Pluralities of wavelength tuning elements are integrated on the chip, one associated with each of the modulated sources. An optical combiner is formed on the PIC chip and the signal outputs of the modulated sources are optically coupled to one or more inputs of the optical combiner and provided as a combined channel signal output from the combiner. The wavelength tuning elements provide for tuning the operating wavelength of the respective modulated sources to be approximate or to be chirped to the standardized wavelength grid. The wavelength tuning elements are temperature changing elements, current and voltage changing elements or bandgap changing elements.

Multiple access performance in UWB systems using time hopping vs. direct sequence spreading

Abstract: Ultra-wideband radio systems operate using extremely short duration signaling pulses. Spread spectrum techniques for multiple access and interference suppression are commonly considered for such systems. We compare time-hopping spread spectrum with pulse position modulation (TH-PPM) and time-hopping/direct-sequence spreading with antipodal signaling (TH/DS-BPSK) in terms of their multiple access performance, and present some arguments for the use of one versus the other in a given system.

Design and performance of 2-D codes for wavelength-time optical CDMA

Abstract: In this letter, we use a depth-first search algorithm to generate two-dimensional (2D) codes with unit auto- and cross-correlation properties for wavelength-time optical code-division multiple access (CDMA) systems. We examine how the code weight and size (number of wavelengths and/or time chips) affect the two important system parameters, namely the error probability (bit-error rate) in terms of multiuser interference and the maximum number of codes that can be generated. We show that 2D wavelength-time optical CDMA systems should use codes with low weight and a high wavelength to time chip ratio. The depth first search algorithm allows us to generate significantly more codes than previously proposed code construction algorithms; when used in conjunction with forward error correction, our approach potentially allows for a large number of simultaneous users operating with a BER<10/sup -9/.

20-mW widely tunable laser module using DFB array and MEMS selection

Abstract: The authors describe a novel configuration for a wavelength selectable laser that provides wide tuning and distributed-feedback (DFB) performance and reliability at a fundamentally low cost structure. The configuration consists of a DFB laser array and a micromechanical mirror that selects one element of the array. The MEMS tilt mirror also loosens the tolerances, since the fine optical alignment is done electronically. Only one laser is operated at a time, with coarse tuning realized by selecting the correct laser and fine tuning by adjusting the chip temperature. The 33-nm total tuning at 20-mW fiber coupled power is obtained in a fully functional module.

Transmitter photonic integrated circuit (TxPIC) chips

Abstract: A photonic integrated circuit (PIC) chip comprising an array of modulated sources, each providing a modulated signal output at a channel wavelength different from the channel wavelength of other modulated sources and a wavelength selective combiner having an input optically coupled to received all the signal outputs from the modulated sources and provide a combined output signal on an output waveguide from the chip. The modulated sources, combiner and output waveguide are all integrated on the same chip.

The ALTRO chip: a 16-channel A/D converter and digital processor for gas detectors

Abstract: The ALTRO (ALICE TPC Read Out) chip is a mixed-signal integrated circuit designed to be one of the building blocks of the readout electronics for gas detectors. Originally conceived and optimised for the Time Projection Chamber (TPC) of the ALICE experiment at the CERN LHC, its architecture and programmability makes it suitable for the readout of a wider class of gas detectors. In one single chip, the analogue signals from 16 channels are digitised, processed. compressed and stored in a multi-acquisition memory. The Analogue-to-Digital converters embedded in the chip have a 10-bit dynamic range and a maximum sampling rate in the range of 20 to 40 MHz. After digitisation, a pipelined hardwired processor is able to remove from the input signal a wide range of systematic and non- systematic perturbations, related to the non-ideal behaviour of lite detector, temperature variation of the electronics, environmental noise, etc. Moreover. the processor is able to suppress the signal tail within 1 /spl mu/s after the pulse peak with 0.1% accuracy thus narrowing the pulses to improve their identification. The signal is then compressed by removing all data below a programmable threshold, except for a specified number of pre- and post-samples around each peak. This produces non-zero data packets. Eventually, each data packet is marked with its time stamp and size - so that the original data can be reconstructed afterwards and stored in lite multi-acquisition memory that has a readout bandwidth of 300 Mbyte/sec. This paper addresses the algorithms of lite implemented digital functions and the performance of the ALTRO chip on measured data.

Apparatus and method for controlling data transmission

Abstract: An interface for controlling the transmission of data between integrated circuit (IC) chips. The interface comprises a data bus for transmitting data from a first integrated circuit chip to a second integrated circuit chip, and a control bus for transmitting control signals between the first and second integrated circuits. The first IC has a memory for receiving data for transmission to the second IC, and the second IC has a scheduler and a data output port, the scheduler being arranged to control the transfer of data from the memory of the first IC to the data output port of the second IC via the data bus. The interface is capable of stopping and reinitiating data transmission on detection of errors in transmitted data, and the interface may include a code transfer bus for transferring error detection code separately from associated data.

Multi-channel communications transceiver

Abstract: A transceiver system according to the present invention transmits data utilizing the baseband and one or more frequency separated transmission bands. A baseband transmitter is combined with one or more transmitters that transmit data into one of the frequency separated transmission bands. A baseband receiver is combined with one or more receivers that receive data from the frequency separated transmission bands. Any combination of modulation systems can be utilized (e.g. PAM for the baseband and QAM for the frequency separated bands). A transceiver circuit or chip according to the present invention includes a transmitter and a receiver and communicates with a corresponding transceiver chip. In some embodiments, one baseband PAM transmitter is combined with one frequency separated QAM transmitter.

Managing on-chip inductive effects

Abstract: With process technology and functional integration advancing steadily, chips are continuing to grow in area while critical dimensions are shrinking. This has led to the emergence of on-chip inductance to be a factor whose effect on performance and on signal integrity has to be managed by chip designers and has to be sometimes traded off against other performance parameters. In this paper, we cover several techniques to reduce on-chip inductance which in turn improve timing predictability and reduce signal delay and crosstalk noise. We present experimental results obtained from simulations of a typical high performance bus structure and a clock tree structure to examine the effectiveness of some of the different inductance reduction techniques.

Radio frequency module

Abstract: In a compact radio frequency module, a first chip forms a heater element and a second chip forms a device whose operating characteristics vary with temperature change or whose maximum operating temperature is lower than the maximum operating temperature of the first chip. A multilayer substrate has a plurality of dielectric layers and a plurality of conductor layers and mechanically supports the first chip and the second chip with some of the conductor layers electrically connected with these chips. The module can conduct the heat generated by the first chip throughout the module; guide the heat generated by the first chip from the module's top face side to its bottom face side; and interrupt the heat conduction from the first conductor pattern on which the first chip is placed to the second conductor pattern on which the second chip is placed.

Circuit for reducing pin count of a semiconductor chip and method for configuring the chip

Abstract: A circuit that reduces external terminal count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration codes, by reducing the number of external input terminals required for generating the configuration data. The circuit includes multiplexers, each of which selects output data or configuration data, and includes an output in communication with a respective external output terminal of the chip. A selector is connectable between a selected one of the external output terminals and an external input terminal in communication with a memory to serially input configuration data on that output terminal to the memory to configure the chip. Thus, configuration codes are generated for the chip using a reduced number of external input terminals, thereby reducing the overall external terminal count of the chip. The circuit and chip may be embodied on a network or Ethernet card.

A smart wind sensor using thermal sigma-delta modulation techniques

Abstract: A smart wind sensor realized in a standard CMOS process combines a two-dimensional thermal flow sensor and three auto-zeroed comparators on a single chip. The comparators form the basis of three thermal sigma-delta modulators that control and digitize the heat distribution in the chip. One modulator maintains the chip at a constant temperature above that of the flow, while the other two cancel orthogonal components of a flow-induced temperature gradient. The bit-stream outputs of the modulators are decimated off-chip and used to determine wind speed and direction. Wind tunnel tests show that the sensor is capable of measuring wind speed and direction with an accuracy of ±4% and ±2°, respectively, over the range 2–18 m/s.

Module for an analysis device, applicator as an exchange part of the analysis device and analysis device associated therewith

Abstract: An analysis device that may be used in biochemical analyses includes a module in a first housing, including a chip support, a sensor chip and electrical contacts between the chip and the chip support. The chip is encapsulated so that the electrical contacts are insulated and the sensitive surface of the sensor chip remains accessible to a fluid to be tested. The module and the first housing form an exchangeable applicator or chip card with mocrofluidic components or functions and is inserted into a second housing that has an evaluation unit for reading and analyzing measured data.

Apparatus and method for leadless packaging of semiconductor devices

Abstract: The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first chip having bond pads with a second chip having bond pads positioned on the first chip to form a vertically stacked package. Interconnections between the bond pads are formed by metallized layers on the package that extend to an edge of the package to join castellations along sides of the package to form a plurality of leadless input/output locations for the package. In one embodiment, the castellations include planar metallized portions. In another embodiment, the castellations include semi-cylindrical metallized portions. In still another embodiment, insulators are positioned between the chips, and on the package base. In still another embodiment, a chip includes a photosensitive device having screening optical layers. Bond pads on the chip are electrically coupled to castellations extending from the bond pads to form leadless input/output locations for the package.

Temperature analysis of continuous-flow micro-PCR based on FEA

Abstract: Continuous-flow micro-PCR chip is a novel method, which is quite different from conventional PCR and micro-chamber PCR chip. A fast and continuous DNA amplification reaction can be obtained by moving the sample through three individual temperature zones whose temperature is constant during the course of reaction. In this paper, temperature patterns of two kinds of continuous-flow micro-PCR: glass–glass-bonding chip and silicon–glass-bonding chip are studied using finite element analysis (FEA). The temperature uniformity and temperature gradient on the chips surface are investigated. Based on analysis results, a simple method that can realize continuous-flow PCR on silicon–glass-bonding chip is introduced. Only denaturation zone is heated and the water is flowed through the renaturation zone and extension zone along a channel. Preliminary experiment is designed to prove the feasibility of the method. And an interface chip is designed to realize multi-times PCR using one chip.