Showing papers on "Clock domain crossing published in 1991"

Exact zero skew

Abstract: An exact zero skew clock routing algorithm using the Elmore delay model is presented. Recursively in a bottom-up fashion, two zero-skewed subtrees are merged into a new tree with zero skew. The algorithm can be applied to single-staged clock trees, multi-staged clock trees, and multi-chip system clock trees. It is ideal for hierarchical methods of constructing large systems. All subsystems can be constructed in parallel and independently, and then interconnected with exact zero skew. Experimental results are presented. >

Spread spectrum communications system

Abstract: A spread spectrum communication system for direct sequence transmission of digital information having a modulation format which is particularly suitable for indoor communication within residential, office and industrial structures. The modulation format combines BPSK or MSK spreading with FM carrier modulation by data bits and a carrier frequency shift whose magnitude is related to both a chip rate and a spreading sequence length. The carrier, chip clock and data clock are all synchronous and the sequence length is an integral submultiple of the bit length. The system reduces the frequency error between the transmitter chip clock and the receiver chip clock to permit the elimination of a code phase tracking loop in the receiver to reduce the receiver complexity. The receiver has an extended dynamic range which makes possible the reception of very strong signal without an automatic gain control loop (AGC) as well as reducing the time needed for code phase acquisition. The transmission system is highly resistant to CW jamming and short distance multipath effects.

Multiple frequency phase-locked loop clock generator with stable transitions between frequencies

Abstract: A phase-locked loop (PLL) clock generator circuit which is capable of changing the frequency of its outpt clock signal in a stable fashion. Selection of the frequency of the output clock signal is made by way of a selectable frequency divider coupled between the reference clock signal and an input of the PLL, with another frequency divider in the feedback loop of the PLL; each of these frequency dividers are selectable according to a signal on a select bus, translated by way of a ROM look-up table. The circuit also includes a multiplexer having a first input coupled to the PLL output, and a second input coupled to a stable clock signal, for example to the referenc clock signal or to the output of a fixed frequency PLL. The conrol input of the multiplexer is controlled by a state machine which monitors the select bus. Responsive to detection of a transition of the select bus, indicating a new frequency, the state machine issues a pulse to the control input of the multiplexer to cause it to select the stable clock signal for sufficient time to allow the PLL to acquire and lock onto the new frequency, after which the multiplexer again selects the PLL output as the output clock signal. As a result, the unstable and non-linear behavior at the PLL output does not appear at the output of the circuit, with a stable clock signal at a safe frequency appearing thereat during the PLL transitional cycles.

Skew-free clock signal distribution network in a microprocessor

Abstract: A clock signal distribution network in a microprocessor for distributing a global clock signal to a plurality of units of the microprocessor includes a clock generator for generating a first clock signal with an input delay A phase locked loop circuit generates a controllable delay to the first clock signal to become the global clock signal A clock driver drives the global clock signal to the plurality of units An electrical connector includes a plurality of connection lines for coupling the global clock signal to the plurality of units A length equalizer equalizes the signal transfer delay of each of the plurality of connection lines such that the global clock signal reaches each of the plurality of units via each of the plurality of connection lines at the same time Each of the plurality of units includes an area buffer for standardizing its input load to the clock driver A dummy buffer introduces the input delay of the clock generator to the global clock signal The phase locked loop circuit controls the generation of the controllable delay to the first clock signal in response to the output signal from the dummy buffer such that the global signal received at each of the plurality of units is synchronized to the clock input signal independent of a process variation, a temperature variation, and a voltage supply variation The method of eliminating clock signal in the clock signal distribution network is also described

Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like

Abstract: A method is provided for eliminating hold time violations in implementing high-speed logic circuits specified in circuit configuration data includes the steps of providing a synchronizer flip-flop device or latch corresponding to every flip-flop device or latch specified in the circuit configuration data. The synchronizer flip-flop is provided immediately upstream in the data path from its corresponding original user flip-flop device. A predetermined amount of delay is added to the user's original clock and data signals. A synchronizing clock signal generator provides a delayed synchronizer clock for each master clock in the circuit which is provided to each user flip flop.

Computer with transparent power-saving manipulation of CPU clock

Abstract: A computer system having power management control features which include states of normal clock speed operation, slow clock speed operation, and stop-clock operation based on input/output activity, system bus activity, and program parameters. The system detects inactivity over a period of time and places the system in one of the states to provide for power conservation and accessibility by a user.

Digital clock buffer circuit providing controllable delay

Abstract: A clock buffer circuit that generates a local clock signal in response to a system clock signal. The clock buffer circuit includes a buffer circuit for generating the local clock signal in response to an intermediate clock signal. A buffer control circuit generates the intermediate clock signal in response to the system clock signal and the local clock signal. The buffer control circuit provides a variable delay so that, with an additional delay provided by the buffer circuit, the local clock signal has a selected phase relationship in relation to the system clock signal.

Synchronous dynamic random access memory

Abstract: A synchronous dynamic random-access memory has transparent latch circuits that latch address signals in synchronization with a clock signal. An X-address is latched following activation of a first control signal; a Y-address is latched following activation of a second control signal. Data selected by the latched X- and Y-addresses are held in a data latch and output through a tri-state output circuit in synchronization with the clock signal. Data output starts a certain number of clock cycles from activation of the first control signal. The data can be output for one clock cycle, the same data can be output for two or more consecutive clock cycles, or different data can be output in consecutive clock cycles in an order determined by certain bits in the X- and Y-addresses.

Semiconductor integrated circuit capable of synchronous and asynchronous operations and operating method therefor

Abstract: A self-timed random-access memory device includes randomly accessible memory circuitry (7), a clock generator (9) responsive to an external clock signal for generating an internal clock signal, an input circuit (8') responsive to the internal clock signal for latching and outputting a supplied input signal, an output circuit (11') responsive to the internal clock signal for latching and outputting an output from the memory device, and circuitry (81, 82, 85, 86; 115, 116, 124, 125; 135, 136, 144, 145) responsive to a through state specifying signal (TH, THM) for disabling the latch function of the input circuit and the output circuit. The memory device can be switched, in response to the through state specifying signal, between a mode operating synchronously with the externally supplied clock signal and another mode operating asynchronously with the externally supplied clock signal.

Low power consuming digital circuit device

Abstract: A method is provided for decreasing the power consumption of a sequential digital circuit having a plurality of states being determined from the current state and the input conditions and entered upon the assertion of a pulse from one or more clocks. The method consists of interrupting the switching created by the clock pulses and maintaining the system in a quiescent state. It is first determined whether a subsequent clock pulse will lead to a change in the state of the circuit. If it will, the circuit either waits for a change in the input conditions and state of the circuit, or changes some of the input conditions, depending on the embodiment of the invention. When a circuit configuration is reached in which further clock pulses will not lead to a change in the state of the circuit, the clock signal(s) are replaced by continuously asserted signals. The feedback loop thus created maintains the current state of the circuit in the absence of a clock signal and prevents further switching in the circuit.

Clock signal latency elimination network

Abstract: A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.

Apparatus for providing a system clock locked to an external clock over a wide range of frequencies

Abstract: A digital phase lock loop circuit for synchronizing the phase of clock signals delivered to devices through clock tree circuitry with the phase of input clock signals including a first delay line, a second delay line, a phase detector circuit, apparatus for transferring the input clock signals through the first delay line to the phase detector circuit, apparatus for transferring the input clock signals through the second delay line and the clock tree circuitry to the phase detector circuit, apparatus responsive to the difference in phase detected between the clock signals transferred through the first and second delay lines for varying the delay of one of the delay lines to bring the clock signals transferred through the first and second delay lines into phase with one another.

Low power cordless magnetic field digitizer with differential grid sensing and synchronous position demodulation

Abstract: A digitizing system includes a tablet and a cordless pointing device including a plurality of data grid conductors in the tablet and a plurality of clock grid conductors in the tablet, all receiving a magnetic field signal transmitted by the pointing device. A data channel circuit includes a differential amplifier and demodulating and filtering circuitry coupled to an output of the differential amplifier, having a clock input. An A/D converter has an input coupled to an output of the demodulating and filtering circuitry. Multiplexing circuitry selectively couples various grid conductor signals to the data channel circuit. A clock recovery circuit responsive to the clock grid conductors includes a phase-locked-loop circuit that generates a recovered clock signal which is synchronous with the magnetic field signal and is used as a reference for demodulating the phase and amplitude of signals multiplexed from the data grid conductors to the data channel circuit. Accurate determination of the pointer tip position is achieved simultaneously with accurate decoding of pointer commands represented by shifts in the frequency of the magnetic field signal.

A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC

Abstract: A GaAs IC that performs clock recovery and data retiming functions in 2.5-Gb/s fiber-optic communication systems is presented. Rather than using surface acoustic wave (SAW) filter technology, the IC employs a frequency- and phase-lock loop (FPLL) to recover a stable clock from pseudo-random non-return-to-zero (NRZ) data. The IC is mounted on a 1-in*1-in ceramic substrate along with a companion Si bipolar chip that contains a loop filter and acquisition circuitry. At the synchronous optical network (SONET) OC-48 rate of 2.488 Gb/s, the circuit meets requirements for jitter tolerance, jitter transfer, and jitter generation. The data input ambiguity is 25 mV while the recovered clock has less than 2 degrees rms edge jitter. The circuit functions up to 4 Gb/s with a 40-mV input ambiguity and 2 degrees RMS clock jitter. Total current consumption from a single 5.2-V supply is 250 mA. >

Independent clocking local area network and nodes used for the same

Abstract: In a local area network composed of transmission lines for interconnecting a plurality of subordinate networks including synchronous apparatuses and a plurality of nodes which connect the subordinate networks to the transmission lines, information is transferred using a fixed length frame, a clock source which generates an independent clock signal and a circuit which generates a fixed length frame with the oscillation frequency of the clock source as a reference are provided in each node so as to adopt an independent clocking system, and distribution of a common synchronizing clock required for synchronous apparatuses is made by transmission while embedding transition point information of a synchronizing clock in a specific space in the fixed length frame. Further, each node generates a fixed length transmission frame with an independent clock signal, and on the other hand, there are provided in each node, from the requirement that information quantity applied to a network is made constant, a circuit for extracting a received clock, a storage device for storing received information temporarily, and an information outgoing quantity control circuit in which information quantity which is sent out in one frame is increased when the information quantity stored in the storage device becomes more than a predetermined first reference value and information quantity which is sent out in one frame is decreased when the information quantity stored in the storage device becomes less than a predetermined second reference value.

Phase and frequency adjustable digital phase lock logic system

Abstract: A phase lock logic system is provided for (i) determining differences in phase and frequency of a received composite clock and data signal with respect to a local clock signal and (ii) providing control signals to enable accurate sampling and reconstruction of the received data. The system includes a delay element which outputs a plurality of phase-delayed signals each being incrementally shifted in phase from the local clock signal. A sorting circuit receives the phase-delayed local clock signals and the incoming composite signal, defines a number of time intervals in each cycle of the local clock signal equal to the number of phase-delayed local clock signals, and sorts positive and negative going transitions in the received composite signal into the defined time intervals. Counters indicate the number of transitions occurring during a selected time interval. A logic circuit reads the counters, determines the differences in frequency and phase of the received composite signal with respect to the local clock signal, and outputs first and second control signals. A barrel shifter responsive to the first control signal selects which of the counters counts the number of transitions occurring in a given time interval. A multiplexer responsive to the first and second control signals extracts the phase-delayed local clock signal which most closely approximates the phase and frequency of the received composite signal. A regenerator compares the extracted signal to the received composite signal and outputs regenerated data.

Self-regulating clock generator

Abstract: There is disclosed a self-regulating clock generator for providing an output clock signal to clock a CMOS microprocessor. The output clock signal has first and second phases of sufficient length to accommodate microprocessor speed paths and is provided in response to an input clock signal having a frequency and a duty cycle within a wide range of frequencies and duty cycles. The clock generator includes a latch arranged to be set and reset by the input clock signal and having an output for providing the output clock signal. A delay circuit is coupled to the latch output and enables the setting and resetting of the latch to establish the phase lengths. Also disclosed is a second clock generator which includes a pair of latches and a pair of delay circuits for providing an output clock signal having first and second phases of different lengths.

Semiconductor apparatus including semiconductor integrated circuit and operating method thereof

Abstract: A semiconductor apparatus including a semiconductor integrated circuit is disclosed. The semiconductor integrated circuit includes a circuit block, a plurality of boundary scan registers, a system data terminal, a test signal terminal and a control circuit. The control circuit responds to a test signal to generate control signals (a select signal LT, shift clock signals SCLK1 and SCLK2, a capture clock signal CPCLK and an update clock signal UPCLK) for controlling the boundary scan registers. The boundary scan registers are connected in cascade to each other and each connected to the circuit block. Each boundary scan register includes a selector circuit (12) and latch circuits (13, 14, 15). The latch circuit (13) responds to the shift clock signal SCLK1 to shift data of an adjacent preceding boundary scan register, an also responds to the update clock signal UPCLK to capture data from the selector circuit (12). The selector circuit (12) responds to the select signal LT to select system data or test data. The latch circuit (14) responds to the shift clock signal SCLK2 to shift the captured data to an adjacent succeeding boundary scan register. The latch circuit (15) responds only to the update clock signal UPCLK to apply the selected data to the circuit block.

A clock buffer with adjustable delay and fixed duty cycle output

Abstract: A clock buffer circuit for a computer system, and a computer system incorporating the same, are disclosed. The clock buffer circuit includes a differential input buffer for receiving the input clock signal, with its output coupled to the input of a phase locked loop (PLL). The switching level of the differential input buffer is adjustable, either by adjusting the DC bias applied to the input clock signal, or by adjusting the reference signal, which changes the point in the cycle of the input clock signal at which the differential buffer switches. The PLL synchronizes its output to an edge of the output of the differential buffer, but maintains the same duty cycle (e. g., 50%). Accordingly, the clock buffer circuit may have its delay adjusted, by modifying a voltage divider, applying a variable voltage, or programmably via a digital-to-analog converter, to match the delays of other clock buffer circuits in the computer system, reducing the clock skew in the system. A sine wave may be used as the input cloak signal, so that harmonic noise is reduced in the system.

Method and apparatus for controlling clock skew

Abstract: A circuit for controlling clock skew has a plurality of delay elements placed in each of the clock output paths in a clock distribution circuit. The delay elements may be selectively switched into or out of each clock output path in order to adjust the delays of each clock output path so that the skew between clock outputs is minimized. The delay in each clock output path is determined by measuring the frequency of a ring oscillator created by connecting a feedback loop across the delay elements. The frequency of oscillation is measured as delay elements are switched into or out of each clock output path until the frequency reaches close to a target frequency.

Method and apparatus for complete functional testing of a complex signal path of a semiconductor chip

Abstract: A test register coupled to an absolute delay regulator circuit of a clock repeater chip enables complete functional testing of a clock delay path of the regulator. The test register is connected to a measurement latch of the clock path in a "logical OR" configuration with respect to a measurement delay line and is enabled during a test mode by control logic of the repeater chip. Operationally, a sequence of logic "0" bits are forced in the measurement delay line during test mode. A state machine clears the measurement latch, and then loads a test pattern into the test register. As each bit of the register is set, a corresponding bit in the measurement latch is also set to simulate a measurement cycle; the results of the "measurement" are stored in the measurement latch. Once the test pattern is loaded, the repeater chip is placed into a measurement test mode. Execution of a measurement test cycle then propagates the test pattern throughout the clock delay path of the regulator. An output clock signal is sampled and if determined present, indicates that the clock path column under test is functional. Each column of the clock path is then tested separately in sequence.

Apparatus and method for recovery of multiphase modulated data

Abstract: A method and apparatus are provided for recovering multiphase modulated data. A signal pulse of a fixed duration is generated upon the transition of a first phase component of a multiphase modulated signal transmitted at a fixed bit rate. A data clock signal having a frequency in synchronism with the bit rate is generated in response to an error signal. The data clock signal is delayed by a delay of approximately one half the duration of the signal pulse. The delayed clock is gated using the signal pulse to provide the error signal that establishes the data clock frequency. Components of the multiphase signal are sampled using the phase locked data clock to recover data.

Clock switching apparatus and method for computer systems

Abstract: A clock switching apparatus is provided in a data processing system which includes a system clock for selectively switching the system clock from a first clock signal to a second clock signal and vice versa. The clock switching apparatus includes a multiplexer coupled to receive the first clock signal and the second clock signal for selectively switching the system clock from the first clock signal to the second clock signal. The multiplexer provides the system clock. A control logic circuit is coupled to receive the second clock signal and a control signal for controlling the multiplexer to switch the system clock from the first clock signal to the second clock signal, wherein the control signal is synchronized to the second clock signal in the control logic circuit to become a synchronized control signal. The multiplexer switches the system clock from the first clock signal to the second clock signal when receiving the synchronized control signal from the control logic circuit. A pass logic circuit is provided for outputting the system clock. The pass logic circuit receives the system clock from the multiplexer. The pass logic circuit is controlled by the control logic circuit to output the system clock such that a glitch-free and minimum transitional period within which the system clock is switched from the first clock signal to the second clock signal is ensured. A method of selectively switching the system clock from the first clock signal to the second clock signal in the data processing system is also described.

Method for self regulating CMOS digital microcircuit burn-in without ovens

Abstract: A burn-in heating circuit for an integrated circuit including a burn-in clock generator for producing a burn-in clock signal that is provided to the clock buffer of the clock distribution system of the integrated circuit. The operating frequency of the burn-in clock is at or close to the maximum frequency that the clock distribution system can reliably sustain with valid logic levels, so that the highest possible self-heating can be achieved by power dissipation in the clock distribution system. A comparator that is responsive to a temperature signal representative of the integrated circuit junction temperature and a signal indicative of the desired burn-in temperature modulates the clock generator so that the junction temperature of the integrated circuit resulting from self heating is close to the desired burn-in temperature.

Digital-to-analog converter with delta-sigma modulation

Abstract: The digital-to-analog conversion apparatus operates in synchronization with a system clock signal having a short period to oversample and delta-sigma-modulate a digital input to produce a requantized digital signal. The system clock signal is mixed with noise leaked back due to the oversampling and delta-sigma modulating operation. The system clock signal is frequency-divided by the rate of one-fourth or less to produce a divided clock signal having a long period and being free of the noise. The requantized digital signal is detected each long period, and is pulse-modulated according to the detected results to generate a pulse signal having the long period. This pulse signal is low-pass-filtered to produce an analog output having improved S/N ratio.

Routing independent circuit components

Abstract: A method and apparatus are disclosed for storing and accessing information of both asynchronous and synchronous devices using, for example, pointers (62, 76) having grey code counters which reduce code conversion logic and which are less susceptible to clock glitches, such as improper clock pulses due to internal circuit timing errors. Because the devices are less clock dependent, they do not require the imposition of critical paths during the placement and routing of a circuit layout. Further, fast and reliable accessing of information stored in memory devices can be achieved by multiplexing (80) output bits addressed, for example, via the aforementioned grey code pointers.

Instantaneous breakless clock switching apparatus

Abstract: A clock switching apparatus includes a first phase synchronizing part for receiving n (n is an integer) input clock signals and for generating n first clock signals respectively related to the n input clock signals. Each of the n first clock signals has a frequency higher than that of a corresponding one of the n input clock signals. A selector selects one of the n first clock signals. A frequency divider generates a second clock signal obtained by frequency-dividing the one of the n first clock signals selected by the selector. A second phase synchronizing part generates an output clock signal synchronized with the second clock signal.

PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor

Abstract: Described is a phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is used to generate an internal clock synchronized to a reference clock from outside the chip. In order to obtain a very wide operation bandwidth, it is proposed that the PCG include a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation circuit varies the oscillation bandwidth of the VCO according to the reference clock frequency, preventing the expected oscillation frequency from being outside the oscillation bandwidth. The PCG is designed and fabricated with 1.0 mu m BiCMOS technology, and it achieves an operation bandwidth of 3 to 90 MHz. >

Asynchronous signal extracting circuit

Abstract: An asynchronous signal extracting circuit for extracting asynchronous signals multiplexed in a synchronization frame, comprising a demultiplexer unit (1) that demultiplexes asynchronous signals and clock signals which are in synchronism with valid data in the asynchronous signals, a buffer memory (2) that writes valid data in the demultiplexed asynchronous signals using the clock signals as write clock signals, a phase-locked loop circuit (3) that forms read clock signals for the memory (2), and a control unit (51 that switches the frequency band of a low-pass filter (4) in the circuit (3) periodically or in response to a detection signal of pointer adjustment. The circuit suppresses low-frequency jitter contained in the read clock signals.

Radio receiver with clock signal controlled to improve the signal to noise ratio

Abstract: In a radio paging receiver comprising a receiving section (11), a decoder section (12), and a CPU (13) for distinguishing a specific one of a plurality of call signals and processing a specific message signal succeeding the specific call signal into a processed message signal, the receiving section is intermittently put into operation. The decoder section is put into operation in accordance with a first clock signal which is supplied from a first clock generator (16). A switching circuit (20) selectively connects the CPU with the first clock generator and a second clock generator (17). More particularly, the CPU is put into operation in accordance with a second clock signal which is supplied from the second generator when the receiving section does not operate. The frequency of the second clock signal is much higher than that of the first clock signal. Therefore, the CPU processes the specific message signal into the processed message signal at a rapid processing speed in accordance with the second clock signal when the receiving section is not put into operation.