Showing papers on "Control reconfiguration published in 1989"

Network reconfiguration in distribution systems for loss reduction and load balancing

Abstract: A general formulation of the feeder reconfiguration problem for loss reduction and load balancing is given, and a novel solution method is presented. The solution uses a search over different radial configurations created by considering switchings of the branch exchange type. To guide the search, two different power flow approximation methods with varying degrees of accuracy have been developed and tested. The methods are used to calculate the new power flow in the system after a branch exchange and they make use of the power flow equations developed for radial distribution systems. Both accuracy analysis and the test results show that estimation methods can be used in searches to reconfigure a given system even if the system is not well compensated and reconfiguring involves load transfer between different substations. For load balancing, a load balance index is defined and it is shown that the search and power flow estimation methods developed for power loss reduction can also be used for load balancing since the two problems are similar. >

Reconfiguration of electric distribution networks for resistive line losses reduction

Abstract: The authors describe a heuristic method for the reconfiguration of distribution networks in order to reduce their resistive line losses under normal operating conditions. The proposed approach is characterized by convergence to the optimum or a near-optimum solution and the independence of the final solution from the initial status of the network switches. The methodology has been implemented in a production-grade computer program, DISTOP (Distribution Network Optimization). The compensation-based power flow technique developed at Pacific Gas and Electric Company for the efficient solution of weakly meshed distribution networks is an essential part of this loss reduction methodology. Important implementation aspects of the methodology and the results of its application to several realistic distribution networks are presented. Numerous test results have indicated that the proposed technique is computationally robust and efficient and, hence, suitable for both planning and operations studies. >

Fault-tolerant array processors using single-track switches

Abstract: An array grid model based on single-track switches is proposed. A reconfigurability theorem is developed to provide the theoretical footing for novel reconfiguration algorithms for the fabrication-time and run-time processing. For fabrication-time yield enhancement, the problem of finding a feasible reconfiguration using global control can be reformulated as a maximum independent set problem. An existing algorithm in graph theory is adopted to solve this problem. The simulations conducted indicate that the algorithm is computationally very efficient; therefore, it may also be applicable to certain run-time fault tolerance. In real-time fault tolerance, the propagation time of data/control signals between the host computer incurred in the global control is often prohibitively long; therefore, only distributed processing is feasible. Based on the same reconfigurability theorem, a distributive reconfiguration algorithm is developed for (asynchronous) array processors. >

Fault Tolerance Through Reconfiguration in VLSI and WSI Arrays

Abstract: Fault tolerance is one of the principle mechanisms for achieving high reliability, high availability in digital systems It is the survival attribute of digital systems This book brings together and discusses the most significant results scattered across the vast field of research in fault tolerance It focuses in particular on reconfiguration techniques and presents the authors' own results in the reconfiguration of processing arrays By means of dedicated arrays, they note, it is possible to build systems that are orders of magnitude more powerful than programmed computers Their treatment of networks and arrays is extensive and has wide applicabilityContents: Introduction Typical Processing Arrays Failure Mechanisms and Fault Models Basic Problems of Fault-Tolerance Through Array Configuration Technologies Supporting Reconfiguration Testing Reconfiguration: An Introduction The Diogenes Approach Reconfiguration for Linear Arrays Graph-Theoretical Approaches to Reconfiguration Local Reconfiguration Global Reconfiguration Techniques: Row/Column Elimination Global Mapping: Index Mapping Reconfiguration Techniques Reconfiguration Based on Request-Acknowledge Local Protocols Reconfiguration of Multiple-Pipeline Structures Some Extensions Toward Time Redundancy Appendix: Reliability Prediction of ArraysR Negrini, M G Sami, and R Stefanelli are researchers at the Politecnico di Milano "Fault Tolerance Through Reconfiguration in VLSI and "I Arrays" is included in the Computer Systems series, edited by Herb Schwetman

Application of precomputed control laws in a reconfigurable aircraftflight control system

Abstract: A self-repairing flight control system concept in which the control law is reconfigured after actuator and/or control surface damage to preserve stability and pilot command tracking is described. A key feature of the controller is reconfigurable multivariable feedback. The feedback gains are designed off-line and scheduled as a function of the aircraft control impairment status so that reconfiguration is performed simply by updating the gain schedule after detection of an impairment. A novel aspect of the gain schedule design procedure is that the schedule is calculated using a linear quadratic optimization-based simultaneous stabilization algorithm in which the scheduled gain is constrained to stabilize a collection of plant models representing the aircraft in various control failure modes. A description and numerical evaluation of a controller design for a model of a statically unstable high-performance aircraft are given.

Polymorphic-torus architecture for computer vision

Abstract: A massively parallel fine-grained SIMD (single-instruction multi-data-stream) computer for machine vision computations is described. The architecture features a polymorphic-torus network which inserts an individually controllable switch into every node of the two-dimensional torus such that the network is dynamically reconfigurable to match the algorithm. Reconfiguration is accomplished by circuit switching and is achieved at fine-grained level. Using both the processor coordinate in the torus and the data for reconfiguration, the polymorphic-torus achieves solution time that is superior or equivalent to that of popular vision architectures such as mesh, tree, pyramid and hypercube for many vision algorithms discussed. Implementation of the architecture is given to illustrate its VLSI efficiency. >

Topology design and bandwidth allocation in ATM nets

Abstract: The design of a P/S network embedded into a backbone facility network is discussed. The problem is formulated as a network optimization problem where a congestion measure based on the average packet delay is minimized, subject to capacity constraints posed by the underlying facility trunks. The variables in this problem are the routing on the express pipes (i.e. the channels that interconnect the P/S modes) and the allocation of bandwidth to such pipes. An efficient algorithm is presented for the solution of the above problem and it is applied to some representative examples. It is shown that for some test cases the congestion measure is substantially reduced with respect to the values obtained when the embedded topology is kept identical to the backbone topology. Dynamic reconfiguration schemes where the embedded topology is periodically adjusted to track the fluctuations in traffic requirements are discussed. >

Detection delays, false alarm rates and the reconfiguration of control systems

Abstract: Systems like unstable aircraft or large space structures are inherently vulnerable to failure of components and their reliability has to be improved through fault-tolerant control: given a set of redundant components, the failed element is diagnosed by a failure detection and isolation (FDI) device and its influence is removed through a reconfiguration of the control algorithms. Performance requirements are then usually expressed in terms of a short detection delay and a low false alarm rate for the FDI function and, for example, stability of the reconfigured system. Linear systems subject to random jumps in parameter values are used to analyse the dynamic behaviour of a fault-tolerant control system and it is found that even a short detection delay and/or a low false alarm rate, when fedback in a reconfigurable control loop, significantly affect stability.

Multiple model adaptive controller for the STOL F-15 with sensor/actuator failures

Abstract: A multiple-model adaptive controller that provides for reconfiguration in response to sensor and/or actuator failures is developed for an approach and landing profile for the short-take-off-and-landing (STOL) F-15 aircraft. Each elemental controller within the multiple model controller is based on a command-generator-tracker/proportional-plus-integral/Kalman-filter design employing reduced-order models, and each assumes a particular system status: no failures or a single failed surface or sensor. Filter residual monitoring is used as the mechanism for selecting the appropriate weighting coefficients for blending the outputs of the elemental controllers. The entire controller is evaluated against a higher order truth model with a selected failure, and the process is repeated for all failure modes of interest. >

Reconfiguration of Electric Distribution Networks for Resistive Line Loses Reduction

Abstract: improved contamination performance for HVDC and HVAC. 5. For the range of post diameter tested, the difference in HVDC contamination performance appears to be insignificant considering the spread in results. 6. HVDC field trial programs are planned to study the performance of semi-conductive glaze post insulators and to study natural wind and rain washing effects on different profiles with conventional glaze. Discusser:W. D. Lampe

Introduction to networking for integrated control systems

Abstract: Integrated control system design, which requires interactions between the disciplines of communication systems and control systems, is introduced. An integrated control system has disparate and spatially distributed subsystems interconnected via a common communication channel. Digital data from sensor to controller and from controller to actuator are multiplexed along with traffic from other control loops and management functions. The asynchronous time-division multiplexing introduces time-varying and possibly stochastic delays in the control loops, degrading system dynamic performance. The analysis of delayed control systems is treated, covering the stochastic Lyapunov method approach, the D-partition method, and the method of steps. >

Reconfiguration of VLSI/WSI mesh array processors with two-level redundancy

Abstract: Reconfiguration schemes for replacing faulty cells (processing elements) with spare cells are introduced for massive parallel rectangular mesh array processors with fine-grained cells. The authors introduce the concept of two-level redundancy as an effective way of using redundant units to reduce the complexity of reconfiguration control circuitry, to limit the length of connecting wires after reconfiguration, and to increase the manufacturing yield and the operation reliability. An optimization technique for allocating the redundant cells into both levels is presented. The operational reliability and manufacturing yield of arrays with two-level redundancy are presented. The yield estimation problem is modeled by an occupancy problem in classical combinatorial analysis. Both distributed and clustered defects are taken into consideration in the yield estimation. >

Methods and apparatus for implementing switched virtual connections (SVCs) in a digital communications switching system

Abstract: Methods and apparatus are set forth for quickly making switched virtual connections (SVCs) in a digital circuit switch that integrates voice and data using common switch, control and distribution equipment. SVCs provide concurrent data connection service from one station device, such as a PC, to other station devices over a single line for each station device where the line may also carry voice and terminal data service. A switch control processor remembers connection requests from station devices and acts on opportunities to utilize available bandwidth in an optimal manner. Dynamic connection reconfiguration techniques allow the system to "scavenge" bandwidth unused by voice or terminal data traffic for SVCs thereby providing the largest possible data rate at any given time. Short signalling messages and indexed values are used in order to speed activation time for previously defined connections while resource allocation is performed by the switch control processor to further enhance system operating speed. The system features (a) reduced connection set up time compared with prior art circuit switch communications systems that need to establish a call each time frames are exchanged; (b) the elimination of expensive concentrators (for example, packet switches); (c) a broadcast channel; (d) enhanced traffic analysis capabilities; and (e) the communication security inherent in circuit switch architectures.

Reconfiguration of VLSI arrays by covering

Abstract: In VLSI arrays, redundant cells are added as spares. The proposed approach is applicable as an offline technique at either production time and/or run time. Reconfiguration is implemented by index mapping using a sequence of two operators. A reconfiguration algorithm which utilizes index mapping is proposed. This algorithm uses a new approach to the assignment problem. It is shown that reconfiguration of fault-free cells is equivalent to a covering of faulty cells by spare cells. It is also established that in a two-dimensional array the optimal spare assignment is given by a maximum matching. This translates to a maximum flow. It is shown that a variation of the matching preserves the optimality of the assignment, while reducing the time complexity of the reconfiguration algorithm Characterization theorems for index mapping and simulation results to substantiate the practicality of the approach are presented. >

Optimal Dynamic Control of Resources in a Distributed System

Abstract: The authors quantitatively formulate the problem of controlling resources in a distributed system so as to optimize a reward function and derive optimal control strategies using Markov decision theory. The control variables treated are quite general; they could be control decisions related to system configuration, repair, diagnostics, files, or data. Two algorithms for resource control in distributed systems are derived for time-invariant and periodic environments, respectively. A detailed example to demonstrate the power and usefulness of the approach is provided.

On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors

Abstract: A study is made of the design of fault-tolerant array processors. It is shown how hardware redundancy can be used in the existing structures in order to make them capable of withstanding the failure of some of the array links and processors. Distributed fault-tolerance schemes are introduced for the diagnosis of the faulty elements, reconfiguration, and recovery of the array. Fault tolerance is maintained by the cooperation of processors in a decentralized form of control without the participation of any type of hardcore or fault-free central controller such as a host computer. Time redundancy is utilized by assigning the functions of the failed processors to fault-free processors. >

On mapping algorithms to linear and fault-tolerant systolic arrays

Abstract: A simple mapping technique is developed to design systolic arrays with limited I/O capability. The technique is used to improve systolic algorithms for some matrix computations on linearly connected arrays of PEs (processor elements) with constant I/O bandwidth. The important features of these designs are modularity with constant hardware in each PE, few control lines, simple data-input/output format, and improved delay time. This technique is extended to design an optimal n square root n-time systolic algorithm for n*n matrix multiplication with O( square root n) I/O bandwidth requirement on a fault-tolerant VLSI model. In this model, the propagation delay is assumed to be proportional to wire length. Fault reconfiguration is achieved by using buffers to bypass faulty PEs, which does not affect the clock rate of the system. The unidirectional flow of control and data assures correctness of the algorithm in the presence of faulty PEs. The design can be implemented on reconfigurable fault-tolerant VLSI arrays using the Diogenes methodology. The present designs are compared to those in the literature and are shown to be superior with respect to I/O format, control, and delay from input to output. >

Applications of knowledge-based programming to power engineering problems

Abstract: Application of knowledge-based expert systems to typical power engineering problems involving diagnosis, control and design is described. A review of prototype projects completed at North Carolina State University serves to demonstrate what is involved in expert system development. The examples include a diagnostic tool for rotating-machine vibration problems, implementation of a distribution-feeder reconfiguration control scheme, and a design aid for distribution-feeder capacitor placement. >

A Highly Adaptable Method of Managing Jets and Aerosurfaces for Control of Aerospace Vehicles

Abstract: An actuator selection procedure is presented which uses linear programming to optimally specify bounded aerosurface deflections and jet firings in response to differential torque and/or force commands. This method creates a highly adaptable interface to vehicle control logic by automatically providing intrinsic actuator decoupling, dynamic response to actuator reconfiguration, dynamic upper bound and objective specification, and the capability of coordinating hybrid operation with multiple actuator families. The objective function minimized by the linear program is adapted to realize several goals; ie. discourage large aerosurface deflections, encourage use of certain aerosurfaces (speedbrake, body flap) as a function of vehicle state, minimize drag, contribute to translational control, and adjust the balance between jet firings and aerosurface activity during hybrid operation. A vehicle model adapted from Space Shuttle aerodynamic data is employed in simulation examples that drive the actuator selection with a six-axis vehicle controller tracking a scheduled reentry trajectory.

Automated setup and reconfiguration for modular fixturing

Abstract: Current trends in manufacturing have identified the need for automation and flexibility in fixture design. The majority of flexible fixturing systems, however, are not well suited for automation. Modular fixtures can be designed to meet the requirements for traditional fixtures in addition to those for modern automation. This paper discusses the issues involved in the automation of modular fixtures with emphasis on automated planning. These issues include proper design, determination of layout requirements, feasibility and automatic reconfiguration. Requirements and guidelines for each issue will first be presented in a general format, and then applied specifically to sheet-metal fixturing.

Reconfiguration techniques in the presence of faulty interconnections

Abstract: A general fault model in which interconnection links as well as processing elements may be faulty is discussed. The general architecture is a rectangular array with a switched-bus interconnection network in which bus segments are the elementary interconnection units. An algorithm that permits the creation of interconnection paths as a catenation of fault-free links is presented. The algorithm is optimum, i.e. given a fault distribution it finds a solution whenever the interconnection structure can support it under given initial constraints. The complexity of the algorithm is evaluated; some criteria for its simplification are discussed. >

Probabilistic Analysis of Yield and Area Utilization of Reconfigurable Rectangular Processor Arrays

Abstract: The increase in the number of components on a single chip has forced the designers and manufacturers to consider carefully, the issues related to the reliability, yield and effective silicon area utilization Several reconfiguration schemes have been suggested in the literature to make a chip fault-tolerant by adding redundancy at various logical and physical levels

Restructuring for fault-tolerant systolic arrays

Abstract: The problem of restructuring systolic arrays with faulty cells is considered. An approach to derive the required data-flow paths and computational sites is proposed. The data skewing requirement, which must be satisfied to find an input schedule, is also discussed. Algorithms to restructure systolic arrays for three different architectures of processing elements are presented. A systematic method to retime the restructured array using additional programmable delays so that the retimed array satisfies the data skewing requirements is developed. >

Reconfigurable multipipelines for vector supercomputers

Abstract: The problem of recovering multipipelines in the presence of faulty stages is addressed. The stages are assumed to be organized in rows and columns. The pipeline stages are alternated with reconfiguring circuitry which is used for bypassing the faulty stages. The pipelines are configured by programming the switches in a distributed manner using fault information available locally. The configuration algorithm is optimal in the sense that it recovers the maximum number of pipelines under any fault pattern. Probabilistic bounds on the delay (the number of bypassed faulty stages) and yield (the number of nonfaulty pipelines recovered) are derived. It is shown that the maximum signal delay in any of the pipelines is O(log m), where m is the initial number of pipelines. A constant fraction of these pipelines can be recovered with the scheme, as opposed to an exponentially decreasing number when no reconfiguration is used. The reconfiguration scheme can also be used to provide fault-tolerant buses on a wafer. >

Compilation techniques for a reconfigurable LIW architecture

Abstract: Matching an application to an architecture in structure and size is a way of achieving higher computation speed. This paper presents a combination of a compiler and a reconfigurable long instruction word (RLIW) architecture as an approach to the matching problem. Configurations suitable for the execution of different parts of a program are determined by a compiler, and code is generated for both reconfiguring the hardware and performing the computation. The RLIW machine, consisting of multiple processing and global data memory modules, effectively utilizes the fine-grained parallelism detected in programs by a compiler. The long word instructions control the operation of processing and memory modules in the system. To reduce the data transfer between processing modules and data memory modules, we provide reconfigurable interconnections among the processing modules which permit direct communication. The compiler uses new techniques, including region scheduling, generation of code for reconfiguration of the system, and memory allocation techniques, to achieve improved performance. Algorithms for packing operations into long word instructions and techniques for effectively assigning memory modules to the operands required by an instruction are developed. Results of the experiments to evaluate the system indicate that speedups of 60–300% can be obtained for both scientific and nonscientific programs. The reconfigurable architecture is responsible for much of the speedup. Also, the results indicate that the major problem of memory bottleneck faced in designing parallel systems is successfully attacked.

Orthogonal mapping: a reconfiguration strategy for fault tolerant vlsi/wsi 2-d arrays+

Abstract: Fault tolerance techniques have been adopted historically in discrete-component computing systems as a consequence of particular applications which demanded high reliability and availability.

Flight Control Reconfiguration Using Model Reference Adaptive Control

Abstract: A simplified multivariable model reference adaptive control (MRAC) is shown to provide control reconfiguration for the AFTI/F16 during single, double, triple, and quadruple control surface failures1. The simplified MRAC is unique in that it may employ a reduced order model and is applicable to unstable nonminimum phase plants. The MRAC is capable of implicitly redistributing the control effort among the aircrafts effective surfaces without explicit knowledge of the failure. The resulting control reconfiguration forces the aircraft to approximate the reference model trajectories. The AFTI/F16 model used for simulations incorporated the nonlinear rate and saturation limited servo dynamics.

Configuration methods and tools for manufacturing systems integration

Abstract: The discussion is based on the work of the Systems Integration (SI) group at Loughborough University which has identified features of a framework or infrastructure for systems integration. The provision of such a framework can form a basis for the specification of integration projects and sub-components in order to permit the interchange, reconfiguration, expansion and transferability of the whole or part solutions so generated. The overall aim is to enable a logical mapping of integration tools, implementations and solutions to physical resources at all phases from manufacturing system inception to operation.

FOCUS: an experimental environment for validation of fault-tolerant systems-case study of a jet-engine controller

Abstract: A simulation environment that allows the run-time injection of transient and permanent faults and the assessment of their impact in complex systems is described The error data from the simulation are automatically fed into the analysis software in order to quantify the fault-tolerance of the system under test The features of the environment are illustrated with case study of a fault-tolerant, dual-configuration real-time jet engine controller The entire controller, described at the logic and functional levels, is simulated, and transient fault injections are performed In the controller, fault detection and reconfiguration are performed by transactions over the communication links The simulation consists of the instructions specifically designed to exercise this cross-channel communication The level of effectiveness of the dual configuration of the system to single and multiple transient errors is measured The results are used to identify critical design aspects from a fault-tolerance viewpoint >