Showing papers on "Division (mathematics) published in 2006"

Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems

Abstract: Preface. About the Authors. 1. Introduction. 1.1 Number Representation. 1.2 Algorithms. 1.3 Hardware Platforms. 1.4 Hardware-Software Partitioning. 1.5 Software Generation. 1.6 Synthesis. 1.7 A First Example. 1.7.1 Specification. 1.7.2 Number Representation. 1.7.3 Algorithms. 1.7.4 Hardware Platform. 1.7.5 Hardware-Software Partitioning. 1.7.6 Program Generation. 1.7.7 Synthesis. 1.7.8 Prototype. 1.8 Bibliography. 2. Mathematical Background. 2.1 Number Theory. 2.1.1 Basic Definitions. 2.1.2 Euclidean Algorithms. 2.1.3 Congruences. 2.2 Algebra. 2.2.1 Groups. 2.2.2 Rings. 2.2.3 Fields. 2.2.4 Polynomial Rings. 2.2.5 Congruences of Polynomial. 2.3 Function Approximation. 2.4 Bibliography. 3. Number Representation. 3.1 Natural Numbers. 3.1.1 Weighted Systems. 3.1.2 Residue Number System. 3.2 Integers. 3.2.1 Sign-Magnitude Representation. 3.2.2 Excess-E Representation. 3.2.3 B's Complement Representation. 3.2.4 Booth's Encoding. 3.3 Real Numbers. 3.4 Bibliography. 4. Arithmetic Operations: Addition and Subtraction. 4.1 Addition of Natural Numbers. 4.1.1 Basic Algorithm. 4.1.2 Faster Algorithms. 4.1.3 Long-Operand Addition. 4.1.4 Multioperand Addition. 4.1.5 Long-Multioperand Addition. 4.2 Subtraction of Natural Numbers. 4.3 Integers. 4.3.1 B's Complement Addition. 4.3.2 B's Complement Sign Change. 4.3.3 B's Complement Subtraction. 4.3.4 B's Complement Overflow Detection. 4.3.5 Excess-E Addition and Subtraction. 4.3.6 Sign-Magnitude Addition and Subtraction. 4.4 Bibliography. 5. Arithmetic Operations: Multiplication. 5.1 Natural Numbers Multiplication. 5.1.1 Introduction. 5.1.2 Shift and Add Algorithms. 5.1.2.1 Shift and Add 1. 5.1.2.2 Shift and Add 2. 5.1.2.3 Extended Shift and Add Algorithm: XY t C t D. 5.1.2.4 Cellular Shift and Add. 5.1.3 Long-Operand Algorithm. 5.2 Integers. 5.2.1 B's Complement Multiplication. 5.2.1.1 Mod Bntm B's Complement Multiplication. 5.2.1.2 Signed Shift and Add. 5.2.1.3 Postcorrection B's Complement Multiplication. 5.2.2 Postcorrection 2's Complement Multiplication. 5.2.3 Booth Multiplication for Binary Numbers. 5.2.3.1 Booth-r Algorithms. 5.2.3.2 Per Gelosia Signed-Digit Algorithm. 5.2.4 Booth Multiplication for Base-B Numbers (Booth-r Algorithm in Base B). 5.3 Squaring. 5.3.1 Base-B Squaring. 5.3.1.1 Cellular Carry-Save Squaring Algorithm. 5.3.2 Base-2 Squaring. 5.4 Bibliography. 6 Arithmetic Operations: Division. 6.1 Natural Numbers. 6.2 Integers. 6.2.1 General Algorithm. 6.2.2 Restoring Division Algorithm. 6.2.3 Base-2 Nonrestoring Division Algorithm. 6.2.4 SRT Radix-2 Division. 6.2.5 SRT Radix-2 Division with Stored-Carry Encoding. 6.2.6 P-D Diagram. 6.2.7 SRT-4 Division. 6.2.8 Base-B Nonrestoring Division Algorithm. 6.3 Convergence (Functional Iteration) Algorithms. 6.3.1 Introduction. 6.3.2 Newton-Raphson Iteration Technique. 6.3.3 MacLaurin Expansion-Goldschmidt's Algorithm. 6.4 Bibliography. 7. Other Arithmetic Operations. 7.1 Base Conversion. 7.2 Residue Number System Conversion. 7.2.1 Introduction. 7.2.2 Base-B to RNS Conversion. 7.2.3 RNS to Base-B Conversion. 7.3 Logarithmic, Exponential, and Trigonometric Functions. 7.3.1 Taylor-MacLaurin Series. 7.3.2 Polynomial Approximation. 7.3.3 Logarithm and Exponential Functions Approximation by Convergence Methods. 7.3.3.1 Logarithm Function Approximation by Multiplicative Normalization. 7.3.3.2 Exponential Function Approximation by Additive Normalization. 7.3.4 Trigonometric Functions-CORDIC Algorithms. 7.4 Square Rooting. 7.4.1 Digit Recurrence Algorithm-Base-B Integers. 7.4.2 Restoring Binary Shift-and-Subtract Square Rooting Algorithm. 7.4.3 Nonrestoring Binary Add-and-Subtract Square Rooting Algorithm. 7.4.4 Convergence Method-Newton-Raphson. 7.5 Bibliography. 8. Finite Field Operations. 8.1 Operations in Zm. 8.1.1 Addition. 8.1.2 Subtraction. 8.1.3 Multiplication. 8.1.3.1 Multiply and Reduce. 8.1.3.2 Modified Shift-and-Add Algorithm. 8.1.3.3 Montgomery Multiplication. 8.1.3.4 Specific Ring. 8.1.4 Exponentiation. 8.2 Operations in GF(p). 8.3 Operations in Zp[x]/f (x). 8.3.1 Addition and Subtraction. 8.3.2 Multiplication. 8.4 Operations in GF(pn). 8.5 Bibliography. Appendix 8.1 Computation of fki. 9 Hardware Platforms. 9.1 Design Methods for Electronic Systems. 9.1.1 Basic Blocks of Integrated Systems. 9.1.2 Recurring Topics in Electronic Design. 9.1.2.1 Design Challenge: Optimizing Design Metrics. 9.1.2.2 Cost in Integrated Circuits. 9.1.2.3 Moore's Law. 9.1.2.4 Time-to-Market. 9.1.2.5 Performance Metric. 9.1.2.6 The Power Dimension. 9.2 Instruction Set Processors. 9.2.1 Microprocessors. 9.2.2 Microcontrollers. 9.2.3 Embedded Processors Everywhere. 9.2.4 Digital Signal Processors. 9.2.5 Application-Specific Instruction Set Processors. 9.2.6 Programming Instruction Set Processors. 9.3 ASIC Designs. 9.3.1 Full-Custom ASIC. 9.3.2 Semicustom ASIC. 9.3.2.1 Gate-Array ASIC. 9.3.2.2 Standard-Cell-Based ASIC. 9.3.3 Design Flow in ASIC. 9.4 Programmable Logic. 9.4.1 Programmable Logic Devices (PLDs). 9.4.2 Field Programmable Gate Array (FPGA). 9.4.2.1 Why FPGA? A Short Historical Survey. 9.4.2.2 Basic FPGA Concepts. 9.4.3 XilinxTM Specifics. 9.4.3.1 Configurable Logic Blocks (CLBs). 9.4.3.2 Input/Output Blocks (IOBs). 9.4.3.3 RAM Blocks. 9.4.3.4 Programmable Routing. 9.4.3.5 Arithmetic Resources in Xilinx FPGAs. 9.4.4 FPGA Generic Design Flow. 9.5 Hardware Description Languages (HDLs). 9.5.1 Today's and Tomorrow's HDLs. 9.6 Further Readings. 9.7 Bibliography. 10. Circuit Synthesis: General Principles. 10.1 Resources. 10.2 Precedence Relation and Scheduling. 10.3 Pipeline. 10.4 Self-Timed Circuits. 10.5 Bibliography. 11 Adders and Subtractors. 11.1 Natural Numbers. 11.1.1 Basic Adder (Ripple-Carry Adder). 11.1.2 Carry-Chain Adder. 11.1.3 Carry-Skip Adder. 11.1.4 Optimization of Carry-Skip Adders. 11.1.5 Base-Bs Adder. 11.1.6 Carry-Select Adder. 11.1.7 Optimization of Carry-Select Adders. 11.1.8 Carry-Lookahead Adders (CLAs). 11.1.9 Prefix Adders. 11.1.10 FPGA Implementation of Adders. 11.1.10.1 Carry-Chain Adders. 11.1.10.2 Carry-Skip Adders. 11.1.10.3 Experimental Results. 11.1.11 Long-Operand Adders. 11.1.12 Multioperand Adders. 11.1.12.1 Sequential Multioperand Adders. 11.1.12.2 Combinational Multioperand Adders. 11.1.12.3 Carry-Save Adders. 11.1.12.4 Parallel Counters. 11.1.13 Subtractors and Adder-Subtractors. 11.1.14 Termination Detection. 11.1.15 FPGA Implementation of the Termination Detection. 11.2 Integers. 11.2.1 B's Complement Adders and Subtractors. 11.2.2 Excess-E Adders and Subtractors. 11.2.3 Sign-Magnitude Adders and Subtractors. 11.3 Bibliography. 12 Multipliers. 12.1 Natural Numbers. 12.1.1 Basic Multiplier. 12.1.2 Sequential Multipliers. 12.1.3 Cellular Multiplier Arrays. 12.1.3.1 Ripple-Carry Multiplier. 12.1.3.2 Carry-Save Multiplier. 12.1.3.3 Figures of Merit. 12.1.4 Multipliers Based on Dissymmetric Br Bs Cells. 12.1.5 Multipliers Based on Multioperand Adders. 12.1.6 Per Gelosia Multiplication Arrays. 12.1.6.1 Introduction. 12.1.6.2 Adding Tree for Base-B Partial Products. 12.1.7 FPGA Implementation of Multipliers. 12.2 Integers. 12.2.1 B's Complement Multipliers. 12.2.2 Booth Multipliers. 12.2.2.1 Booth-1 Multiplier. 12.2.2.2 Booth-2 Multiplier. 12.2.2.3 Signed-Digit Multiplier. 12.2.3 FPGA Implementation of the Booth-1 Multiplier. 12.3 Bibliography. 13. Dividers. 13.1 Natural Numbers. 13.2 Integers. 13.2.1 Base-2 Nonrestoring Divider. 13.2.2 Base-B Nonrestoring Divider. 13.2.3 SRT Dividers. 13.2.3.1 SRT-2 Divider. 13.2.3.2 SRT-2 Divider with Carry-Save Computation of the Remainder. 13.2.3.3 FPGA Implementation of the Carry-Save SRT-2 Divider. 13.2.4 SRT-4 Divider. 13.2.5 Convergence Dividers. 13.2.5.1 Newton-Raphson Divider. 13.2.5.2 Goldschmidt Divider. 13.2.5.3 Comparative Data Between Newton-Raphson (NR) and Goldschmidt (G) Implementations. 13.3 Bibliography. 14 Other Arithmetic Operators. 14.1 Base Conversion. 14.1.1 General Base Conversion. 14.1.2 BCD to Binary Converter. 14.1.2.1 Nonrestoring 2p Subtracting Implementation. 14.1.2.2 Shift-and-Add BCD to Binary Converter. 14.1.3 Binary to BCD Converter. 14.1.4 Base-B to RNS Converter. 14.1.5 CRT RNS to Base-B Converter. 14.1.6 RNS to Mixed-Radix System Converter. 14.2 Polynomial Computation Circuits. 14.3 Logarithm Operator. 14.4 Exponential Operator. 14.5 Sine and Cosine Operators. 14.6 Square Rooters. 14.6.1 Restoring Shift-and-Subtract Square Rooter (Naturals). 14.6.2 Nonrestoring Shift-and-Subtract Square Rooter (Naturals). 14.6.3 Newton-Raphson Square Rooter (Naturals). 14.7 Bibliography. 15. Circuits for Finite Field Operations. 15.1 Operations in Zm. 15.1.1 Adders and Subtractors. 15.1.2 Multiplication. 15.1.2.1 Multiply and Reduce. 15.1.2.2 Shift and Add. 15.1.2.3 Montgomery Multiplication. 15.1.2.4 Modulo (Bk2c) Reduction. 15.1.2.5 Exponentiation. 15.2 Inversion in GF(p). 15.3 Operations in Zp[x]/f (x). 15.4 Inversion in GF(pn). 15.5 Bibliography. 16. Floating-Point Unit. 16.1 Floating-Point System Definition. 16.2 Arithmetic Operations. 16.2.1 Addition of Positive Numbers. 16.2.2 Difference of Positive Numbers. 16.2.3 Addition and Subtraction. 16.2.4 Multiplication. 16.2.5 Division. 16.2.6 Square Root. 16.3 Rounding Schemes. 16.4 Guard Digits. 16.5 Adder-Subtractor. 16.5.1 Alignment. 16.5.2 Additions. 16.5.3 Normalization. 16.5.4 Rounding. 16.6 Multiplier. 16.7 Divider. 16.8 Square Root. 16.9 Comments. 16.10 Bibliography. Index.

Existence of a solution to the cell division eigenproblem

Abstract: We consider the cell division equation which describes the continuous growth of cells and their division in two pieces. Growth conserves the total number of cells while division conserves the total mass of the system but increases the number of cells. We give general assumptions on the coefficient so that we can prove the existence of a solution (λ, N, ϕ) to the related eigenproblem. We also prove that the solution can be obtained as the sum of an explicit series. Our motivation, besides its applications to the biology and fragmentation, is that the eigenelements allow to prove a priori estimates and long-time asymptotics through the General Relative Entropy.16.

Better Ways to Cut a Cake

Abstract: Procedures to divide a cake among n people with n-1 cuts (the minimum number) are analyzed and compared. For 2 persons, cut-and-choose, while envy-free and efficient, limits the cutter to exactly 50% if he or she is ignorant of the chooser’s preferences, whereas the chooser can generally obtain more. By comparison, a new 2person surplus procedure (SP), which induces the players to be truthful in order to maximize their minimum allocations, leads to a proportionally equitable division of the surplus—the part that remains after each player receives 50%—by giving each person exactly the same proportion of the surplus as he or she values it. For n ≥ 3 persons, a new equitable procedure (EP) yields a maximally equitable division of a cake. This division gives all players the highest common value that they can achieve and induces truthfulness, but it may not be envy-free. The applicability of SP and EP to the fair division of a heterogeneous, divisible good, like land, is briefly discussed.

Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition

Abstract: Logarithmic number systems (LNS) offer a viable alternative in terms of area, delay, and power to binary number systems for implementing multiplication and division operations for applications in signal processing. The Mitchell algorithm (MA), proposed, reduces the complexity of finding the logarithms and the antilogarithms using piecewise straight line approximations of the logarithm and the antilogarithm curves. The approximations, however, result in some loss of accuracy. Thus, several methods have been proposed in the literature for improving the accuracy of Mitchell's algorithm. In this work, we investigate a new method based on operand decomposition (OD) to improve the accuracy of Mitchell's algorithm when applied to logarithmic multiplication. In the OD technique proposed, for reducing the amount of switching activity in binary multiplication, the two inputs to be multiplied are together decomposed into four binary operands and the product is expressed as the sum of the products of the decomposed numbers. We show that applying operand decomposition to the inputs as a preprocessing step to Mitchell's multiplication algorithm significantly improves the accuracy. Experimental results indicate that the proposed algorithm for logarithmic multiplication reduces the error percentage of Mitchell's algorithm by 44.7 percent on the average. It is also shown that the OD method yields further improvement when combined with the other correction methods proposed in the literature

Fast Decimal Floating-Point Division

Abstract: A new implementation for decimal floating-point (DFP) division is introduced. The algorithm is based on high-radix SRT division The SRT division algorithm is named after D. Sweeney, J. E. Robertson, and T. D. Tocher. with the recurrence in a new decimal signed-digit format. Quotient digits are selected using comparison multiples, where the magnitude of the quotient digit is calculated by comparing the truncated partial remainder with limited precision multiples of the divisor. The sign is determined concurrently by investigating the polarity of the truncated partial remainder. A timing evaluation using a logic synthesis shows a significant decrease in the division execution time in contrast with one of the fastest DFP dividers reported in the open literature

Complex interval arithmetic using polar form

Abstract: In this paper, the polar representation of complex numbers is extended to complex polar intervals or sectors; detailed algorithms are derived for performing basic arithmetic operations on sectors. While multiplication and division are exactly defined, addition and subtraction are not, and we seek to minimize the pessimism introduced by these operations. Addition is studied as an optimization problem which is analytically solved. The complex interval arithmetic thus defined is illustrated with some numerical examples which show that in many applications, the polar representation is more advisable.

Low power digital media broadcast receiver with time division

Abstract: Systems and methods for providing a low power receiver device using fine grained time division are provided. In one embodiment, the receiver device comprises a tuner, a demodulator configured to demodulate at least one sampled signal, a payload processor configured to process at least one demodulated signal into an output format, and a time division control logic configured to generate a control signal to switch at least one component within the receiver device between modes to conserve power. The at least one component may be switched between an active mode, a standby mode, a power off mode, and a low power mode. In further embodiments, the at least one component may be switched between staggered modes.

Image processor and image processing method

Abstract: PROBLEM TO BE SOLVED: To easily deform a photographic subject on an image by resizing at least a part of the image. SOLUTION: This image processor resizing at least the part of the image has: a division part dividing the image into a plurality of division images in a specific direction; a resizing part resizing at least one of the plurality of division images in the specific direction at an arbitrary ratio; and an image composition part recombining the plurality of division images including the resized division image to generate a composite image. COPYRIGHT: (C)2008,JPO&INPIT

A note on 2-local maps

Abstract: The aim of this note is to characterize 2-local automorphisms and derivations on matrix rings over finite-dimensional division rings.

A region-dividing approach to robust semidefinite programming and its error bound

Abstract: A new asymptotically exact approach is presented for robust semidefinite programming, where coefficient matrices polynomially depend on uncertain parameters. Since a robust semidefinite programming problem is difficult to solve directly, an approximate problem is constructed based on a division of the parameter region. The optimal value of the approximate problem converges to that of the original problem as the resolution of the division becomes finer. An advantage of this approach is that an upper bound on the approximation error is available before solving the approximate problem. This bound shows how the approximation error depends on the resolution of the division. Furthermore, it leads to construction of an efficient division that attains small approximation error with low computational complexity. Numerical examples show efficacy of the present approach. In particular, an exact optimal value is often found with a division of finite resolution.

Optimal Proliferation Rate in a Cell Division Model

Abstract: We consider a size structured cell population model where a mother cell gives birth to two daughter cells. We know that the asymptotic behavior of the density of cells is given by the solution to an eigenproblem. The eigenvector gives the asymptotic shape and the eigenvalue gives the exponential growth rate and so the Maltusian parameter. The Maltusian parameter depends on the division rule for the mother cell, i.e., symmetric (the two daughter cells have the same size) or asymmetric. We use a min-max principle and a differentiation principle to find the variation of the first eigenvalue with respect to a parameter of asymmetry of the cell division. We prove that the symmetrical division is not always the best fitted division, i.e., the Maltusian parameter may be not optimal.

Portable terminal and its display control method

Abstract: PROBLEM TO BE SOLVED: To properly execute a plurality of applications even in a portable terminal whose resources are limited. SOLUTION: As operation modes, a whole picture mode for assigning a whole display picture to one application; a focus switching mode for switching a focus between a plurality of division areas to which each application is assigned; and a small picture mode for updating the display content of the division area according to the execution of the application in the focused division area are prepared. The operation mode is switched according to the operation of the operation part. The execution of the application is permitted only in the focused division area between the plurality of division areas, and the content of the application is reduced and displayed in the division area. When the focus is moved from the division area, a final picture displayed in the division area is stored, and the execution of the application is interrupted and ended, and data necessary for restoring the state in interruption are saved. COPYRIGHT: (C)2008,JPO&INPIT

Patch having easily detachable release sheet

Abstract: A patch permitting division of only its release sheet by simply pulling right and left, wherein detachment of the release sheet is easy. There is provided a patch comprising a stretchable support, a plaster applied substantially all over one major surface of the support and a release sheet attached to the whole surface of the plaster wherein only the release sheet is divided at a division zone by simply pulling right and left, and wherein one or two or more precut parts that open when the patch is pulled right and left are disposed in the neighborhood on the division zone.

Print control method capable of managing functions incorporated in printing device

Abstract: When a printer driver of a user's PC connected to a printing device is activated, it transmits user information, division information and the like to the printing device, and inquires about any restriction on its functions. The printer driver acquires, from the printing device, information regarding a restriction set on a user or on a division, a restriction due to a configuration and a restriction set for a period, as well as a message input by an administrator. It displays the functions of the printing device on a screen presented upon activation of the driver, in such a manner that the function of which the use is restricted is grayed out to indicate that the function is unusable, and also displays the type of the restriction and the corresponding message input by the administrator.

A method of homomorphic encryption

Abstract: The existing homomorphic encryption scheme is based on ring of the integer, and the possible operators are restricted to addition and multiplication only. In this paper, a new operation is defined—Similar Modul. Base on the Similar Modul, the number sets of the homomorphic encryption scheme is extended to real number, and the possible operators are extended to addition, subtraction, multiplication and division. Our new approach provides a practical ways of implementation because of the extension of the operators and the number sets.

Space Efficient Division on FPGAs

Abstract: Division algorithms are discussed in the context of implementing image processing algorithms on FPGAs. The speed requirements of image processing are modest, but throughput is important, with one division having to be completed per clock cycle. Several division algorithms are compared, with the non-restoring algorithms being both the smallest and fastest of the basic methods. If necessary, the algorithms may be easily pipelined to meet the throughput requirements.

Division points on subvarieties of isotrivial semi-abelian varieties

Abstract: The positive characteristic function-field Mordell-Lang conjecture for finite rank subgroups is resolved for curves as well as for subvarieties of semiabelian varieties defined over finite fields. In the latter case, the structure of the division points on such subvarieties is determined.

Graphic engine for approximating a quadratic bezier curve in a resource-constrained device

Abstract: A method is provided for approximating a quadratic Bezier curve represented by two anchor points and a control point that are fixed-point binary numbers. If a first flatness of a line formed between the two anchor points of the Bezier curve is less than a threshold, the method includes replacing the Bezier curve with an edge between the two anchor points. If the first flatness is not less than the threshold, the method includes subdividing the Bezier curve into halves and determining a second flatness of one of the halves. The first flatness is approximated by a triangular area formed by the two anchor points and the control point, and the triangular area is approximated by multiplication and subtraction operations. The second flatness of the half is approximated as the triangular area divided by 8, where the division by 8 is determined by shifting 3 bits to the right.

Multiple star wavelength division multiplexing passive optical networks using a wavelength assignment method

Abstract: The present invention discloses a multiple star wavelength division multiplexing passive optical network system using a wavelength assignment method. In a multiple star wavelength division multiplexing passive optical network system using a wavelength assignment method according to the present invention, only one WDM-PON system can provide services for a plurality of subscribers who is distributed in a wide range of area through multiple starring, by setting one or more band for transmitting up-stream signals as an up-stream basic band and one or more band for transmitting down-stream signals as a down stream basic band, respectively, and by dividing each of the up-stream basic band and the down stream basic band into a plurality of wavelength sub-bands and assigning the divided sub-bands to different areas using a wavelength division multiplexer/de-multiplexer which splits a band into two or more sub-bands.

A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics Systems

Abstract: A low-power, area-efficient 128-bit multifunction arithmetic unit has been developed for programmable shaders for handheld 3-D graphics systems. It adopts the logarithmic number system (LNS) at the arithmetic core for the single cycle throughput and the small-size low-power unification of various complex arithmetic operations such as power, logarithm, trigonometric functions, vector multiplication, division, square root and inner product. An uneven 24-piecewise logarithmic conversion scheme is proposed with 0.8% of maximum conversion error. A 93K gate test chip is fabricated with 0.18-?m CMOS technology. It operates at 210MHz with 15.3mW power consumption at 1.8V.

Research on Grid Division and Encoding of Spatial Information Multi-Grids

Abstract: This paper introduces briefly the achievements on global grid research firstly,a new method of grid division is proposed along with several extended method to fit for various research domains.At last,the author expounds the encoding strategy of grids and the conversion method between grid code and coordinate.

Wireless multiple access system for suppressing inter-cell interference

Abstract: An OFDM based multiple access system provides strong persistence against selective frequency fading and further provides suppression of inter-cell interference by using cell differentiating scrambling codes. Thus, the OFDM system maximizes frequency reuse rate. The present invention includes an OFDM modulator (30) frequency-division-multiplexing data to be transmitted, a code division unit (32) multiplexing the frequency-division-multiplexing data with a prescribed code, and an RF end (33) converting the data multiplexed by the code division unit to a radio frequency signal to tansmit. Accordingly, the present invention raises the degree of freedom (frequency division, time division, code division) of system implementation in the multiple access system. The OFDM system includes the scambling of the downlink data by different scrambling codes by a cell unit for base stations within at least two neighboring cells to identify the respective cells and transmitting the spread downlink data.

Real-time arithmetic unit

Abstract: In this paper we discuss the paradigm of real-time processing on the lower level of computing systems. An arithmetical unit based on this principle containing addition, multiplication, division and square root operations is described. The development of the computation operators model is based on the imprecise computation paradigm and defines the concept of the adjustable calculation of a function that manages delay and the precision of the results as an inherent and parameterized characteristic. The arithmetic function design is based on well-known algorithms and offers progressive improvement in the results. Advantages in the predictability of calculations are obtained by means of processing groups of k-bits atomically and by using look-up tables. We report an evaluation of the operations in path time, delay and computation error. Finally, we present an example of our real-time architecture working in a realistic context.

Cooperative Multiple-Access in Fading Relay Channels

Abstract: Virtual antenna arrays can be constructed via relaying even in the case that there is insufficient physical space or other resources for multiple antennae on wireless nodes. When there is a multiple access scenario, relaying offers a variety of ways to establish communication between source and destination nodes. We will compare a scheme based on space division multiple access to previously studied time division based ones. We observe that space division improves especially the ergodic capacity.

Moving image division apparatus, caption extraction apparatus, method and program

Abstract: A moving image division apparatus includes (A) a storage unit configured to store a 3-dimensional spatio-temporal image containing a plurality of video frames arranged in time order, (B) an extraction unit configured to extract a plurality of line segments parallel to a time axis in a slice image, the slice image being acquired by cutting the spatio-temporal image along a plane parallel to the time axis and (C) a division unit configured to divide the spatio-temporal image into a plurality of scenes based on a temporal domain of the line segment.

Characteristic time series and operation region of the system of two tank reactors (CSTR) with variable division of recirculation stream

Abstract: The paper deals with a system of a cascade of two tank reactors, being characterized by the variable stream of recirculating fluid at each stage. The assumed mathematical model enables one to determine the system’s dynamics for the case when there is no time delay and for the opposite case. The time series of the conversion degree and of the dimensionless fluid temperature, characteristic for the system considered as well as the operation regions—the latter—basing on Feingenbaum diagrams with respect to the division ratio of the recirculating stream are presented.

Voltage control method based on soft partitions in power system

Abstract: The invention relates to a voltage control method for electric system basing on soft division The method comprises: real time data gathering in electrical network; partition online; establishing CSVC mathematical model for control area; calculating the control quantity of each CSVC mathematical model; outputting the control quantity of each control area; returning to circulating for CSVC controlling when the CSVC control cycle time out

FPGA implementation of the conjugate gradient method

Abstract: The rational fraction number system is proposed to solve the algebraic problems in FPGA devices. The fraction number consists of the n-bit integer numerator and the n -bit integer denominator, and can represent numbers with 2n bit mantissa. Experimental linear equation system solver was developed in FPGA device, which implements the recursive conjugate gradient method. Its hardware arithmetic unit can calculate addition, multiplication, and division of fraction numbers with n=35 in a pipelined mode. The proposed unit operates with the band matrices with the dimensions up to 3500.

Hardware Implementation of Finite-Field Division

Abstract: Algorithms for performing divisions over Z p and GF(p m ) are described, the corresponding digital circuits are synthesized and conclusions about their computation times are drawn. The results of their implementation within field-programmable devices are given in the case of the most efficient ones.

Image processing method

Abstract: PROBLEM TO BE SOLVED: To provide an image processing method which makes it possible to obtain an image which has high quality and a high resolution without leaving boundaries of adjacent blocks detectable visually even in a case where the image has already been subjected to the processing of resolution enhancement (enlargement) of the image using a set of fractal parameters SOLUTION: The image processing apparatus 100 includes: an image division unit 114 which divides an input image IN into range blocks using L (L is an integer of 2 or more) numbers of division patterns so that at least one of the boundaries of each region in a division pattern varies from the boundaries of each region in the other division patterns; a parameter calculation unit 103 which calculates a set of fractal parameters of each range block of the input image IN so as to obtain L sets of fractal parameters; an image transformation unit 107 which generates L pieces of fractal transformed images using, one by one, the modified sets of fractal parameters obtained according to enlargement ratios; and an image synthesis unit 112 which synthesizes the L pieces of transformed images so as to generate a single synthesized image The image transformation unit 107 and the image synthesis unit 112 repeat the transformation and synthesis using in sequence the respective sets of fractal parameters until this synthesized image converges COPYRIGHT: (C)2006,JPO&NCIPI