Showing papers on "Effective number of bits published in 2007"

An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes

Abstract: A resolution-rate scalable ADC for micro-sensor networks is described. Based on the successive approximation register (SAR) architecture, this ADC has two resolution modes: 12 bit and 8 bit, and its sampling rate is scalable, at a constant figure-of-merit, from 0-100 kS/s and 0-200 kS/s, respectively. At the highest performance point (i.e., 12 bit, 100 kS/s), the entire ADC (including digital, analog, and reference power) consumes 25 muW from a 1-V supply. The ADC's CMRR is enhanced by common-mode independent sampling and passive auto-zero reference generation. The efficiency of the comparator is improved by an analog offset calibrating latch, and the preamplifier settling time is relaxed by self-timing the bit-decisions. Prototyped in a 0.18-mum, 5M2P CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 65 dB (10.55 ENOB) and an SFDR of 71 dB. Its INL and DNL are 0.68 LSB and 0.66 LSB, respectively

A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS

Abstract: A fully dynamic SAR ADC is proposed that uses passive charge-sharing and an asynchronous controller to achieve low power consumption. No active circuits are needed for high-speed operation and all static power is removed, offering power consumption proportional to sampling frequency from 50MS/s down to 0. The prototype implementation in 90nm digital CMOS achieves 7.8 ENOB, 49dB SNDR at 20MS/s consuming 290 muW. This results in a FOM of 65fJ/conversion-step.

Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors

Abstract: This paper presents a CMOS imager with a column-parallel ADC architecture based on a multiple-ramp single-slope (MRSS) ADC. Like the well-known column-level single-slope ADC, an MRSS ADC uses a very simple analog column circuit, which mainly consists of an analog comparator and some switches. A prototype imager using the MRSS ADC architecture was realized in a 0.25 CMOS process. Measurements demonstrate that the conversion speed of an MRSS ADC is 3.3 higher than a single-slope ADC while dissipating only 16% more power. Furthermore, the MRSS ADC can be easily adapted to exhibit a companding characteristic, which exploits the amplitude-dependent nature of the photon shot noise present in imager signals. Measurements show that the resulting multiple-ramp multiple-slope ADC is 25% faster than an MRSS ADC while dissipating the same amount of power.

A Fine Resolution TDC Architecture for Next Generation PET Imaging

Abstract: A fine resolution and process scalable CMOS time-to-digital converter (TDC) architecture is presented. A 6-bit fine resolution TDC design using the new architecture is evaluated for positron emission tomography (PET) imaging application. The TDC architecture uses a hierarchical delay processing structure to achieve single cycle latency and high speed of operation. The fine resolution converter, realized in 130 nm CMOS, is designed to operate over a reference clock frequency of 500 MHz but can be scaled to multi GHz operation through time interleaving. Without external calibration, the TDC is used as a 5-bit fine resolution converter with 4.65 ENOB (effective number of bits). Under this condition, the 6-bit TDC has an INL (integral non-linearity) measurement of less than 1.45 LSB and a DNL (differential non-linearity) measurement of less than 1.25 LSB. With external calibration, a reduction of more than 50% in INL/DNL nonlinearities is demonstrated improving the ENOB to 5.5 bits, pushing the TDC to a 6-bit fine resolution operation. The TDC has a 31 ps timing resolution and power consumption of less than 1 mW. The design is believed to be the fastest and the lowest power consuming fine resolution TDC in the literature.

A 4-GS/s 4-bit Flash ADC in 0.18- $\mu{\hbox {m}}$ CMOS

Abstract: A 4-bit noninterleaved flash ADC implemented in 0.18-mum digital CMOS achieves a sampling rate of 4 GS/s. A 32 mum by 32 mum, on-chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4GS/s, respectively. The ADC achieves a bit error rate of less than 10-11 at 4 GS/s.

A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse

Abstract: Power and area saving concepts such as operational amplifier (opamp) bias current reuse and capacitive level shifting are used to lower the analog power of a 10-bit pipelined analog-to-digital converter (ADC) to 220 muW/MHz. Since a dual-input bias current reusing opamp performs as two opamps, the opamp summing nodes can be reset in every clock cycle. By using only N-channel MOS (NMOS) input stages, the capacitive level shifter simplifies the gain-boosting amplifier design and enables fast opamp settling with low power-consumption. The prototype achieves 9.2/8.8 effective number of bits (ENOB) for 1- and 20-MHz inputs at 50 MS/s. The ADC works within the temperature range of 0deg to 85 degC and the supply voltage from 1.62 to 1.96 V with little measured loss in the ENOB. The chip consumes 18 mW (11 mW for the analog portion of the ADC and 7 mW for the rest including buffers) at 1.8 V, and the active area occupies 1.1 times 1.3 mm2 using a 0.18-mum complementary metal oxide semiconductor (CMOS) process.

Method and system for application of unequal error protection to uncompressed video for transmission over wireless channels

Abstract: A method and system of wireless communication is provided which involves inputting information bits, wherein certain bits have higher importance level than other bits, and applying unequal protection to the bits at different importance levels. As such, important bits are provided with more protection for transmission and error recovery. Applying unequal protection involves using skewed constellations such that more important bits are provided with more error recovery protection.

All-Optical Analog-to-Digital Conversion Based on Polarization-Differential Interference and Phase Modulation

Abstract: A novel approach of an all-optical analog-to-digital converter is proposed and demonstrated. One single-phase modulator and a continuous-wave laser diode are used to quantize the sinusoidal tone analog signal. Software sampling measurements yielded an effective number of bits of 4.1. Benefits of the proposed setup are its simple design, high bandwidth, and stability. The scheme is primarily limited in the optical domain by the speed of the phase modulator and in electronic domain by electrical comparators and logic devices

Thermometer-to-binary decoders for flash analog-to-digital converters

Abstract: Decoders for low power, high-speed flash ADCs are investigated. The sensitivity to bubble errors of the ROM decoder with error correction, ones-counter, 4-level folded Wallace-tree, and multiplexer-based decoder are simulated. The ones-counter and multiplexer-based decoder, corresponding to the error insensitive and hardware efficient cases, are implemented in a 130 nm CMOS SOI technology. Measurements yield an ENOB of about 4.1 bit for both, and energy consumption of 80 pJ and 60 pJ, for the respective decoders. Hence we conclude that the MUX-based decoder seems to be a good choice with respect to area, efficiency, and speed.

Majority voter circuits and semiconductor devices including the same

Abstract: A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.

Communication Limits with Low Precision Analog-to-Digital Conversion at the Receiver

Abstract: We examine the Shannon limits of communication systems when the precision of the analog-to-digital conversion (ADC) at the receiver is constrained. ADC is costly and power- hungry at high speeds, hence ADC precision is expected to be a limiting factor in the performance of receivers which are heavily based on digital signal processing. In this paper, we consider transmission over an ideal discrete-time real baseband additive white Gaussian noise (AWGN) channel, and provide capacity results when the receiver ADC employs a small number of bits, generalizing our prior work on one bit ADC. We show that dithered ADC does not increase capacity, and hence restrict attention to deterministic quantizers. To compute the capacity, we use a dual formulation of the channel capacity problem, which is attractive due to the discrete nature of the output alphabet. The numerical results we obtain strongly support our conjecture that the optimal input distribution is discrete, and has at most one mass point in each quantizer interval. This implies, for example, that it is not possible to support large alphabets such as 64-QAM using 2-bit quantization on the I and Q channels, at least with symbol rate sampling.

A 1.35 GS/s, 10b, 175 mW time-interleaved AD converter in 0.13 μm CMOS

Abstract: A time-interleaved ADC is presented with 16 channels, each consisting of two successive approximation (SA) ADCs in a pipeline configuration. Three techniques are presented to increase the speed of an SA-ADC. Single channel performance is 6.9 ENOB at an input frequency of 4 GHz. Multi-channel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz and a FoM of 0.6 pJ/conversion-step.

An Ultra-Wideband 7-Bit 5 Gsps ADC Implemented in Submicron InP HBT Technology

Abstract: An ultra-wideband 7-bit 5-Gsps analog-to-digital converter (ADC), fabricated in a 4-level interconnect, 0.8 mum Indium-Phosphide (InP) heterojunction bipolar transistor (HBT) technology, is presented. This monolithic folding/interpolating ADC includes a front-end master-slave sample and hold and a pipeline stage sample and hold. The chip achieves 6 effective number of bits (ENoB) Nyquist performance at a sample rate of 5 Gsps, while dissipating 8.4 W. Furthermore, an ENoB performance of greater than 5.7 is maintained at analog input frequencies up to 7.5 GHz. This effective resolution-bandwidth product performance is significantly higher than any other previously reported monolithic ADC with sample rate ges 3 Gsps.

A 7b 1.1GS/s Reconfigurable Time-Interleaved ADC in 90nm CMOS

Abstract: A time-interleaved pipeline ADC is designed with the reconfigurable resolution and sampling rate, Fs, to accommodate different operation scenarios. The main offset and gain mismatches between four sub-ADCs are modulated to the frequency of F/2 by the reference-and opamp-sharing techniques. Fabricated in 90 nm CMOS, the 7 bit ADC has an ENOB of 6.5 at 1.1 GHz sampling rate. The I/Q ADCs totally consume power of 92 mW from a 1.3 V supply.

Method of digital video reference frame compression

Abstract: The digital video referencing frame image is compressed block by block by applying lossless compression algorithm to pixel components with full length, or 1 bit, 2 bits, 3 bits or 4 bits LSB bits truncation. If a sub-block has high complexity which results in more than 3 bits error for most pixel components, a transfer algorithm with quantization and VLC coding is applied to compress this sub-block. Should the complexity is higher than a threshold or at least one sub-block having error of more than 3 bits for most pixel components, truncating 1 LSB bit of sub-block with simple pattern to save more bits to be allocate to code the sub-block with highest complex pattern.

Method and apparatus for encoding channel quality indicator and precoding control information bits

Abstract: A method and apparatus for encoding channel quality indicator (CQI) and precoding control information (PCI) bits are disclosed. Each of the input bits, such as CQI bits and/or PCI bits, has a particular significance. The input bits are encoded with a linear block coding. The input bits are provided with an unequal error protection based on the significance of each input bit. The input bits may be duplicated based on the significance of each input bit and equal protection coding may be performed. A generator matrix for the encoding may be generated by elementary operation of conventional basis sequences to provide more protection to a most significant bit (MSB).

Digital Domain Measurement and Cancellation of Residue Amplifier Nonlinearity in Pipelined ADCs

Abstract: Digital correction and calibration techniques have been extensively used to cancel linear circuit imperfections in pipelined analog-to-digital converters (ADCs). The self-calibration technique proposed in this paper provides a means of measuring and canceling nonlinear errors of interstage amplifiers in the digital domain. The calibration of nonlinearity coefficients is based on pseudorandom signal modulation and evaluation of digital code histograms. The scheme does not introduce additional precision hardware or test signals and operates in the background without interrupting normal converter operation. The simulation results of a 12-bit ADC show that the calibration is capable of improving the effective number of bits from 7 to 11.8 while achieving parameter adaptation time constants on the order of 100 ms at a sampling rate of 100 MS/s.

Pseudo-multiple sampling methods, systems and devices for analog-to-digital conversion

Abstract: An analog signal is converted to a digital value having a given number of bits that define given quantization levels, by repeatedly sampling the analog signal at a resolution that is less than that which is defined by the given number of bits. Lower resolution sampling results are thereby obtained. The lower resolution sampling results are summed to obtain the digital value having the given number of bits.

A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V 0.13μm CMOS

Abstract: A 10b 205MS/S IF sampling pipelined ADC is fabricated in 1.2/3.3V 0.13μm CMOS. Power consumption and die area are improved by using single-stage opamps throughout the pipeline chain; digital calibration compensates for the reduced stage gain. Foreground calibration is used to shorten the start-up time and background calibration is used afterwards. The ADC has ENOB of 9.0, ERBW of 330MHz, dissipates 92.5mW, and occupies 0.52mm2.

Sigma-delta column-wise A/D conversion for cooled ROIC

Abstract: Designing a digital IR focal plane array (IRFPA) requires fulfilling very stringent requirements in terms of power consumption, silicon area and speed. Among the various ADC architectures like successive approximation, ramp or over-sampled converters, the best choice strongly depends on the application. We believe that sigma-delta converters, in spite of their quite high power consumption, are a promising solution for high-performance and medium size FPA, e.g. 320x240. This paper presents the design of a second-order incremental sigma-delta ADC dedicated to cooled (77K) IRFPA applications. System-level simulations used to define the modulator parameters and specify its analog building blocks are presented. Circuit design of the switched-capacitor modulator and the digital decimation filter is described. The column ADC including the filter has been implemented in a standard 0.35μm CMOS process on the basis of a 25μm pitch and lead to a total length of 3200μm. Test chips including a single ADC have been manufactured end of 2006. The first measurement results, at 77K, are presented along with perspectives and future developments. They demonstrate the following performance: 81dB Signal-to-Noise Ratio (SNR), 13 bits Effective Number Of Bits (ENOB) and 270μW power consumption at 17kSamples/s rate.

A 10b 160MS/s 84mW 1V Subranging ADC in 90nm CMOS

Abstract: A 10b 160MS/S subranging ADC with THA is implemented in a 90nm digital CMOS process. Noise averaging and an auto-zeroed comparator are used in the fine converter to achieve low noise and offset at low power dissipation. The prototype converter achieves an ENOB of 9.1b for an 80MHz input and consumes 84mW from a 1V supply

On Dynamic Range of Digital Receivers

Abstract: Dynamic range of a digital receiver is determined by its analog and mixed signal portion (AMP). Among parameters that characterize the receiver dynamic range, single-tone dynamic range and two-tone dynamic range are usually most important. The ultimate value of the dynamic range upper bound is limited by acceptable power consumption of the receiver AMP. Since expanding the dynamic range usually significantly increases the receiver power consumption, ability to calculate the minimum required dynamic range is very important. An approach to a closed-form solution of the problem is discussed in this paper. Another problem discussed in the paper is achieving the maximum potential dynamic range of a digital receiver. This requires combined use of both well-known and novel methods of dynamic range improvement. The methods include proper selection of the receiver sampling frequency, filtering and utilization of the signal energy during sampling, reduction of the quantization step and increase in the effective number of bits in the receiver A/D, rejection of the strongest interfering signal as close as possible to the antenna, etc.

Class D analog-to-digital converter

Abstract: A new analog-to-digital (ADC) circuit and architecture and the corresponding method of implementation are provided. The analog input signal is converted into a modulated pulse stream such as by a pulse-width-modulation scheme. The time-duration width of the pulses are measured by a TDC (time-to-digital converter) and converted to a digital binary representation that is directly correlated with the voltage amplitude of the analog input signal. The circuit implementation is substantially free of switches and circuit issues such as associated with sigma-delta and switched-capacitor techniques for ADC's.

Pipelined analog-to-digital converter and method of analog-to-digital conversion

Abstract: A pipelined analog-to-digital converter (ADC) has a multistage structure, and the pipelined ADC includes a plurality of stages that form the multistage structure. Each of the stages includes a sample-and-hold (S/H) circuit, a flash ADC, and a digital-to-analog converter (DAC). The S/H circuit converts an analog input signal to a digital signal. The flash ADC detects a digital bit corresponding to the analog input signal. The DAC converts the digital signal to an analog signal, and amplifies a residue signal, which is a difference between the input analog signal and the converted analog signal, that is provided as an analog input signal of the next stage.

8/9 and 8/10-bit encoding to reduce peak surge currents when writing phase-change memory

Abstract: Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The memory cell's reset current can be double a set current, causing peak currents to depend on write data. When all data bits are reset to the amorphous state, a very high peak current is required. To reduce this worst-case peak current, the data is encoded before storage in the PCM cells. An 8/10 encoder adds 2 bits but ensures that no more than half of the data bits are reset. An 8/9 encoder adds an indicator bit, and inverts the 8 bits to ensure that no more than half of the bits are reset. The indicator bit indicates when the 8 bit are inverted, and when the 8 bits are un-inverted. Peak currents are thus reduced by encoding to reduce reset data bits.

A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration

Abstract: A 1.8 V 10 b 210 MS/s CMOS pipelined ADC in 0.18 um CMOS process is presented. The low power consumption at high sampling rate is achieved by using an opamp-sharing technique in 2.5 b/stage pipelined ADC architecture. The opamp settling behavior is well controlled through a regulated switch driving scheme. The clever arrangement of capacitor array renders superior SFDR for the same given systematic mismatch. With a 20 MHz input signal, the ADC achieves 85.9 dB SFDR and 9.57 ENOB at 210 MS/s. Better than 76 dB SFDR and 9.5 ENOB performance is maintained for input frequency up to 100 MHz. The ADC core power consumption is 140 mW at 1.8 V supply. The active die area of ADC core is 1.5 mm2.

A 1V 5-Bit 5GSample/sec CMOS ADC for UWB Receivers

Abstract: This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistors sizes for the cascaded stages are inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for measurements. This chip has been fabricated in 0.13-mum 1P8M CMOS process and the total power consumption is 113 mW with IV supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200 MHz at 5-GSample/sec.

Entropy source for random number generation

Abstract: In a device having a data channel, in which random numbers are needed, such as a data storage device that uses random numbers to generate keys for cryptographic applications, random numbers are generated by a deterministic random bit generator seeded by bits derived from noise on the channel itself. The bits may be extracted from the least significant bits of the data signal after it is digitized, because those bits correspond to the noise in the signal. The extraction may occur immediately after digitization, or after subsequent filtering. A data signal emulator may be provided to simulate a data signal if a seed is required at a time when there is no data activity on the channel. The extracted bits may be post-processed to remove bias before the seed is provided to the deterministic random bit generator.

20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process

Abstract: This paper describes a novel low power 10-bit 125 Msps pipelined ADC implemented in 65 nm standard digital CMOS process. Proposed ADC implements 2.5 b/stage with amplifier shared between consecutive stages, achieves best in class FOM of 0.27 pJ/step with conversion power of 0.16 mW/Msps. The ADC amplifier employs novel techniques of adaptive biasing and cross coupled compensation to achieve improved settling behavior with significant power efficiency. This ADC occupies 0.13mm area and achieves maximum 0.3 LSB DNL and 0.6 LSB INL along with 9.26 ENOB at 125 Msps dissipating 20 mW power from 1.2v supply.