Proceedings ArticleDOI
20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process
Pratap Narayan Singh,Ashish Kumar,Chandrajit Debnath,Rakesh Malik +3 more
- pp 189-192
TLDR
This paper describes a novel low power 10-bit 125 Msps pipelined ADC implemented in 65 nm standard digital CMOS process that employs novel techniques of adaptive biasing and cross coupled compensation to achieve improved settling behavior with significant power efficiency.Abstract:Â
This paper describes a novel low power 10-bit 125 Msps pipelined ADC implemented in 65 nm standard digital CMOS process. Proposed ADC implements 2.5 b/stage with amplifier shared between consecutive stages, achieves best in class FOM of 0.27 pJ/step with conversion power of 0.16 mW/Msps. The ADC amplifier employs novel techniques of adaptive biasing and cross coupled compensation to achieve improved settling behavior with significant power efficiency. This ADC occupies 0.13mm area and achieves maximum 0.3 LSB DNL and 0.6 LSB INL along with 9.26 ENOB at 125 Msps dissipating 20 mW power from 1.2v supply.read more
Citations
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Journal ArticleDOI
Distributed In-Memory Computing on Binary RRAM Crossbar
TL;DR: Based on numerical results for fingerprint matching that is mapped on the proposed RRAM-crossbar, the proposed architecture has shown 2.86x faster speed, 154x better energy efficiency, and 100x smaller area when compared to the same design by CMOS-based ASIC.
Journal ArticleDOI
High-speed and low-power electro-optical DSP coprocessor
TL;DR: In this paper, a fast, power-efficient electro-optical vector-by-matrix multiplier (VMM) architecture is presented to overcome bottlenecks encountered by previous VMM architectures.
Proceedings ArticleDOI
An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar
TL;DR: Based on numerical results for fingerprint matching that is mapped on the proposed RRAM-crossbar, the proposed architecture has shown 2.86x faster speed, 154x better energy efficiency, and 100x smaller area when compared to the same design by CMOS-based ASIC.
Proceedings ArticleDOI
Digital background calibration of a 0.4-pJ/step 10-bit pipelined ADC without PN generator in 90-nm digital CMOS
TL;DR: A simple, yet accurate, digital background calibration technique is proposed to minimize the power dissipation in the digital calibration unit and achieves the same convergence speed and accuracy as PN-based techniques in 2-path (split) pipelined ADCs.
Journal ArticleDOI
Systematic design approach for a gain boosted telescopic OTA with cross-coupled capacitor
TL;DR: A symbolic analysis is presented to study a gain-boosted telescopic operational transconductance amplifier (OTA) with cross-coupled capacitor (positive feedback) across an auxiliary op-amp and it is shown that UGBW, PM and settling behaviour of the OTA can be tuned by the PFC.
References
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Journal ArticleDOI
A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
Boris Murmann,Bernhard E. Boser +1 more
TL;DR: In this article, the authors proposed a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages, achieving more than 60% residue amplifier power savings over a conventional implementation.
Journal ArticleDOI
A pipelined 5-Msample/s 9-bit analog-to-digital converter
Stephen H. Lewis,Paul R. Gray +1 more
TL;DR: A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology.
Proceedings ArticleDOI
Comparator-based switched-capacitor circuits for scaled CMOS technologies
TL;DR: A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design of analog and mixed-signal circuits in scaled CMOS technologies.
Journal ArticleDOI
A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR
TL;DR: A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described.
Journal ArticleDOI
Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies
TL;DR: A comparator-based switched-capacitor (CBSC) design method for sampled-data systems utilizes topologies similar to traditional opamp-based methods but relies on the detection of the virtual ground using a comparator instead of forcing it with feedback.