Showing papers on "Effective number of bits published in 2023"

Analysis of Bandwidth Reduction and Resolution Improvement for Photonics-Assisted ADC

Abstract: To keep pace with increasing data rates in the worldwide communication networks and the increased bandwidths requirements in measurement devices, sensors, radar, and many other applications, photonics-assisted analog-to-digital converters (PADCs) may be promising alternatives to circumvent the bandwidth bottleneck in pure electronic analog-to-digital converters (EADCs). Here we analyze optical sub-Nyquist orthogonal sampling with sinc-pulse sequences for the time-interleaving of high-bandwidth input signals into parallel low-bandwidth sub-signals (first sampling stage). These sub-signals are then detected and further processed with low-bandwidth electronic devices in parallel branches (second sampling stage). Orthogonal sampling with ideal devices is error-free. Additionally, in contrast to electronic sample and hold circuits, the first sampling stage is based on a multiplication and not a switching. Therefore, it adds no aperture jitter and the low jitter of today's oscillators can be directly transferred to the sampling of high-bandwidth signals. Compared to the direct detection, in simulations and a proof of concept experimental demonstration, we show around 8.5 dB signal-to-noise and distortion (SINAD) and 1.4 bit effective number of bits (ENOB) improvement for the detection of a 14.5 GHz signal with the proposed method in a three-branch system. With further simulations we analyze the possibilities and limits of the method and derive an equation for the resolution. In a nine-branch system with a jitter of 10 fs for the oscillator and 100 fs for the electronics, 100 GHz input signals can be processed with a resolution of 6 bit in 11 GHz electronics, for instance. The scheme is only based on a modulator and standard RF equipment. Therefore, integration into a single chip, together with the following electronic ADCs is straightforward.

A Wireless Headstage System Based on Neural-Recording Chip Featuring 315 nW Kickback-Reduction SAR ADC

Abstract: Wireless neural-recording instruments eliminate the bulky cables in multi-channel signal transmission, while the system size should be reduced to mitigate the impact on freely-moving animals. As the battery usually dominates the system size, the neural-recording chip should be low power to minimize the battery in long-termly monitoring. In general, a neural-recording chip consists of an analog front end (AFE) and an 8 bit -10 bit analog-to-digital converter (ADC), while it's challenging to design an ADC with an 8 -10 effective number of bits (ENOB) and sub- μ W power consumption due to the kickback noise. In this work, we propose a kickback-reduction technique for a successive-approximation-register (SAR) ADC based on neural-recording chip. Fabricated in 65 nm CMOS process, the proposed technique reduce the ADC power to 315 nW, resulting in an 8-channel neural-recording chip with 249 μW in total. Measured results show that the chip achieves an ADC ENOB of 9.73 bits, as well as an AFE gain of 43.3 dB and input-referred noise (IRN) of 9.68 μVrms in a bandwidth of 0.9 Hz -7.2 kHz. Combined with a BLE chip and a PCB antenna, the chip is implemented into a 2.6 g wireless headstage system (w/o battery), and an in-vivo demonstration is conducted on a male Sprague-Dawley rat with Parkinson's disease. The headstage system transfers the in-vivo neural signals to a commodity smartphone through BLE, and the miniature size induces little impact on freely-moving activities.

A Multiple Interpolation Algorithm to Improve Resampling Accuracy in Data Triggers

Abstract: To address the problem of low trigger accuracy during trigger resampling and variable sampling rate trigger resampling using a fixed sampling rate analog-to-digital converter (ADC), this paper proposes an interpolation method combining sinc interpolation and linear interpolation to improve accuracy, based on a digital trigger. After behavior simulation verification and actual field programmable gate array (FPGA) test verification, the data collected by two 3GSps 12-bit ADCs were subjected to 8-times sinc interpolation followed by 16-times linear interpolation processing, after which the original trigger resampling accuracy was increased by 128 times and the sampling rate could be realized to vary between 100 MHz and 1 GHz. A signal–noise ratio (SNR) of 46.80 dBFS, a spurious free dynamic range (SFDR) of 45.91 dB, and an effective number of bits (ENOB) of 7.48 bits were obtained by direct trigger resampling without algorithm processing in the behavior simulation. Meanwhile, an SNR of 58.98 dBFS, an SFDR of 60.96 dB, and an ENOB of 9.42 bits were obtained by trigger resampling after algorithm processing. Due to the influence of analog link signal loss and signal interference on the development board, an SNR, SFDR and ENOB of 51.97 dBFS, 61.26 dB, and 8.32 bits, respectively, were obtained from the trigger resampling in the FPGA test. The experimental results show that the algorithm has not only improved the triggering accuracy but has also improved the SNR, SFDR, and ENOB parameters.

A Single-Step Subranging Relaxation Oscillator-Based Open-Loop Sigma-Delta ADC

Abstract: This paper presents a novel subranging Sigma-Delta ADC using a relaxation Current-Controlled Oscillator (ICO). The instantaneous frequency of the ICO at the sampling instant determines its time resolution and hence its quantization error, while its average frequency determines its power dissipation. Therefore, running the ICO at nominally lower frequency for most of the sampling period while increasing its frequency close to the sampling instant achieves high resolution and low power consumption. This idea is similar to the strategy employed by athletes in a race where they speed-up close to the finish line to gain a clear lead from others. A prototype ADC is designed and fabricated in TSMC 180nm CMOS technology. It achieves an ENOB of 11.9 bits consuming $10~\mu \text{W}$ of power from a 1.8V supply and occupies an active area of 0.06 mm 2, which corresponds to a Schreier FoM of 156.8 dB and a Walden FoM of 625 fJ/conversion cycle.

Massive MIMO Systems with Low-Resolution ADCs: Achievable Rates and Allocation of Quantization Bits

Abstract: In massive multiple-input multiple-output (MIMO) systems, the large number of high-resolution analog-to-digital converters (ADCs) lead to high hardware cost and power consumption. In this work, the uplink achievable rates of massive MIMO systems with low-resolution ADCs are studied with consideration of both “Uniform-ADC” that uses ADCs with the same number of quantization bits and “Mixed-ADC” that allows the use of ADCs with different resolutions. By leveraging an additive quantization noise model (AQNM), the asymptotic achievable rates are obtained for maximum ratio combining (MRC), zero-forcing (ZF), and linear minimum mean squared error (LMMSE) receivers in very simple forms. Taking advantages of the theoretical results, we propose two criteria for allocation of quantization bits. It is found that the optimal quantization bits allocation for LMMSE is Mixed-ADCs with number of quantization bits that are polarized, while Uniform-ADC is optimal for MRC and ZF. When there is a constraint on the total ADC power consumption, the proposed quantization-bit allocation scheme for LMMSE becomes Uniform-ADC when the transmit signal-to-noise ratio (SNR) is below a threshold, which is related to the system scale and the ADC power consumption. The theoretical results are verified by Monte-Carlo simulations.

Design of Self-Calibration Comparator for 12-Bit SAR ADCs

Abstract: A novel self-calibration comparator for a 12-bit 2.5 MSPS successive approximation register analog-to-digital converter (SAR ADC) applied in a touch microcontroller unit (MCU) with small area, high precision, fast response speed, and low-voltage detection is proposed in this paper. A combination of input/output offset storage (IOS/OOS) and an offset trimming circuit was employed to reduce the offset of the cascade preamplifier and the operational transconductance amplifier (OTA), a novel offset trimming circuit with a 5-bit digital controller was designed to further reduce the residual offset voltage, and an improved self-calibration technology was also implemented to compensate the conversion error in SAR ADC system to a minimum. Simulation and measured results show that the input-referred offset calibrating range is ±9.15 mV at 0.61 mV/step, the low-voltage detection of SAR ADC is realized by compensating the conversion error to a minimum, and the effective number of bits (ENOB) and figure of merit (FoM) at 5 V supply and 2.5 M/s rate in the 12-bit SAR ADC with a 95 nm CMOS are 11.33 bits and 726.6 fJ/conversion-step, respectively. The proposed self-calibration comparator applied in the SAR ADC system can automatically eliminate the offset voltage caused by nonidealities and meet the requirements of the touch MCU.

Design of Low-Power High Performance SAR Analog-To-Digital Converter Based on MOS Capacitor DAC Structure

Abstract: In this article, a 5-bit 20 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with 4.53 bits ENOB and 29.0 dB SNDR is designed using 90 nm CMOS process technology using CADENCE virtuoso. This SAR ADC consumes power of 31.67 µW with the figure-of-merit (FoM) 68.54 fJ/conv-step. A modified dynamic comparator with two inverters connected at the output to avoid metastable state of sampled signal is used, which also helps in reducing power consumption. A binary-weighted charge redistribution digital-to-analog converter (DAC) is used using metal oxide semiconductor (MOS) capacitor to lessen the power dissipation also less area requirement as compared to conventional metal–insulator-metal (MIM) capacitor-based DAC. This SAR ADC has potential application for low power and low to medium sampling rate biomedical devices.

Design of a 14-bit Pipelined ADC using Ring Amplifier

Abstract: With the progress of integrated circuit technology, the intrinsic gain of transistors has become increasingly low, and the power consumption and complexity of OTA operational amplifiers have become higher, increasing the overall design difficulty of pipeline ADC. In order to improve the gain of the operational amplifier, improve the overall accuracy of the ADC, and reduce circuit power consumption, a 14-bit 20MSPS analog-to-digital converter with a pipeline structure of 2.5bit-2.5bit-2.5bit-2.5bit-2.5bit-2.5bit-2.5bit-2.5bit-2bit was designed using the SMIC 40nm process and analog drive digital technology under a 1.2V power supply voltage based on a new type of ring amplifier.The simulation results show that the SNDR of the input low-frequency signal pipeline ADC is 70.47dB, the SFDR is 85.5dB, and the ENOB is 11.45bit. When inputting high-frequency signals, the SNDR of the pipeline ADC is 68.35dB, the SFDR is 81.3dB, and the ENOB is 11.07bit.

A Σ-Δ Modulator Based on an Inverter-based Integrator with Dynamic Current Switch

Abstract: This paper presents a low-power high-resolution 3rd-order 1-bit Σ-Δ modulator based on an inverter-based integrator with a dynamic current switch. To reduce the power consumption of the modulator circuit, a dynamic current switch branch is added to form a low-power inverter-based integrator. A 3rd-order 1-bit Σ-Δ modulator is designed in a TSMC 65 nm CMOS technology to verify the effectiveness of the proposed integrator circuit. The prototype Σ-Δ modulator achieves 102.4 dB SNDR, 16.71 Bit ENOB in a 2 KHz signal BW at an Over Sampling Ratio (OSR) of 160, while consuming only 29.5-μW. And the FOMSNDR is 180.7 dB.

A Low-power Level-Crossing ADC for Biosignal Acquisition

Abstract: A large number of redundant signals will be generated when the traditional Nyquist sampling method is used to acquire a biological signal, leading to a system’s energy loss. A new level-crossing analog-to-digital converter (LC-ADC) with non-uniform sampling and fixed window structure is presented, with fewer data and low power consumption features. The circuit uses a 6-bit capacitive DAC to quantize the input signal, avoiding the error accumulation of the 1-bit capacitive DAC structure, and a nanoamp CMOS current bias circuit to provide a very low quiescent current for the comparator, further reducing power consumption. The structure was verified in a 0.18μm CMOS technology. The results indicate that the total power dissipation is 0.26uw@500Hz, the signal-to-noise distortion ratio (SNDR) is 59dB@500Hz, and ENOB reached 9.51bit, which is suitable for the acquisition of low-frequency biological signals.

Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining

Abstract: We describe the advantages and challenges encountered during the design of wideband continuous-time pipeline (CTP) analog-to-digital converters (ADCs). The converter incorporates an area-and power-efficient foreground technique that exploits thermal noise to estimate the taps of digital reconstruction filters of the pipeline. The design features a half-rate mode that exploits the sharp filtering characteristic of the CTP to reduce the back-end sampling rate, thereby lowering power dissipation. The techniques are applied to a CTP that realizes the equivalent of a cascade of a 106-MHz bandwidth sixth-order Butterworth filter followed by a 12.5-bit 800-MS/s ADC. The CTP, realized in 65-nm CMOS, achieves an ENOB of about 12 bits in a 100-MHz bandwidth and dissipates 59 mW from a 1.2-V supply.

Orthogonal Sampling based Broad-Band Signal Generation with Low-Bandwidth Electronics

Abstract: High-bandwidth signals are needed in many applications like radar, sensing, measurement and communications. Especially in optical networks, the sampling rate and analog bandwidth of digital-to-analog converters (DACs) is a bottleneck for further increasing data rates. To circumvent the sampling rate and bandwidth problem of electronic DACs, we demonstrate the generation of wide-band signals with low-bandwidth electronics. This generation is based on orthogonal sampling with sinc-pulse sequences in N parallel branches. The method not only reduces the sampling rate and bandwidth, at the same time the effective number of bits (ENOB) is improved, dramatically reducing the requirements on the electronic signal processing. In proof of concept experiments the generation of analog signals, as well as Nyquist shaped and normal data will be shown. In simulations we investigate the performance of 60 GHz data generation by 20 and 12 GHz electronics. The method can easily be integrated together with already existing electronic DAC designs and would be of great interest for all high-bandwidth applications.

A Single-Channel Voltage-Scalable 8-GS/s 8-b >37.5-dB SNDR Time-Domain ADC With Asynchronous Pipeline Successive Approximation in 28-nm CMOS

Abstract: This article presents a single-channel voltage-scalable 8-GS/s 8-b time-domain analog-to-digital-converter (TD-ADC). It breaks the speed limit of traditional TD-ADC by leveraging asynchronous pipeline successive approximation (APSA), which reduces the quantization period to approximate one-stage time-domain comparator decision time. A co-design methodology of voltage-to-time converter (VTC) and time-to-digital converter (TDC) is proposed to optimize the ADC linearity without increasing the complexity or power consumption, reducing the linearity request of VTC. In addition, concurrent charge redistribution and voltage pull-up is deployed in the VTC, supporting the rail-to-rail input and enabling voltage scalability. The TD-ADC is fabricated in 28-nm CMOS and occupies an active area of 0.011 mm2, demonstrating 39.2-dB signal-to-noise-distortion ratio (SNDR) and 56.1-dB spurious-free dynamic range (SFDR) at 0.9 V, 8-GS/s with 85.3-mW power dissipation and 37.6-dB SNDR and 56.3 dB SFDR at 0.7 V, 5.05 GS/s with 23.1-mW power dissipation, achieving 143.1- and 74.3-fJ/conv.-step Nyquist Walden figure of merit (FoMW), respectively.

An expandable 36‐channel neural recording ASIC with modular digital pixel design technique

Abstract: This paper presents the design and implementation of an expandable neural recording ASIC for multiple-channel neural recording applications. The ASIC consists of 36 modular digital pixels (MDPs) and a global digital controller (GDC) circuit. Each MDP has an analog frontend (AFE) circuit, a 12-bit successive approximation register ADC (SAR ADC), and a local digital controller (LDC) circuit. It achieves 5.9-μV input referred noise (IRN), 10.8-effective number of bits (ENOB), 37.8-μW power consumption, and 0.095 mm2 area per channel. The ASIC is implemented in commercial SMIC 0.18-μm CMOS process and validated by in-vivo experiment on a lab mouse with a 36-channel silicon-based neural probe.

Photonic sampled and quantized analog-to- digital converters on thin-film lithium niobate platform

Abstract: In this paper, an on-chip photonic sampled and quantized analog-to-digital converter (ADC) on thin-film lithium niobate platform is experimentally demonstrated. Using two phase modulators as a sampler and a 5×5 multimode interference (MMI) coupler as a quantizer, a 1 GHz sinusoidal analog input signal was successfully converted to a digitized output with a 20 GSample/s sampling rate. To evaluate the system performance, the quantization curves together with the transfer function of the ADC were measured. The experimental effective number of bits (ENOB) was 3.17. The demonstrated device is capable of operating at a high frequency over 67 GHz, making it a promising solution for on-chip ultra-high speed analog-to-digital conversion.

Comparator‐noise‐based residue measurement and correction technique in 16 bit 1 MS/s SAR ADC

Abstract: This letter presents an accuracy enhancement technique utilized in 16 bit fully differential successive-approximation-register analog-to-digital converters (SAR ADC). For noise performance improvement to obtain a higher ENOB, the residue measurement technique which statistically estimates the input residual error of comparator with Gaussian noise fitting is presented. The ADC digital output is compensated by the residue measurement results. It is verified in the 0.18-μm 1P5M 5 V CMOS process. Finally, a 93.1 dB SNR and a 110.5 dB SFDR are measured operating at 1 MS/s with a 10-kHz input tone and larger than 1-dB SNR improvement is obtained in different chips.

A 0.5-V 10-bit Asynchronous SAR ADC with Monotonic Switching for Biomedical Applications

Abstract: In recent years, it is possible to observe a quickly adoption and daily use of wearable electronic devices such as smart watches and bracelets. Such devices have dedicated systems for monitoring biological signals, such as heartbeat and blood oxidation, and some of these devices already have the ability to provide measurements of electrocardiogram (ECG) and blood pressure signals. Additionally, these devices also feature wireless connection via Bluetooth orWi-Fi communication protocols. Both modern instrumentation and communication systems require the digitization of analog signals by means of analog-to-digital convertes (ADCs) for further digital signal processing. This work presents the design of a Successive Approximation Register (SAR) ADC for low voltage applications with 10 bits and 5 kSPS in asynchronous operating mode. The ADC is designed in 180-nm CMOS technology and operates at a nominal supply voltage of 0.5 V. Schematic-level simulations indicate that the ADC reaches a signal-to-noise-to-distortion (SNDR) ratio of 61.36 dB, leading to an effective number of bits (ENOB) of 9.90 bits. The spurious-free dynamic range (SFDR) is 73.19 dB, and the total power consumption of the ADC is 1.43 μW.

A 121 dB SNDR Zoom ADC Using Dynamic Amplifier and Asynchronous SAR Quantizer

Abstract: This paper presents a discrete-time zoom analog-to-digital converter (ADC) for low-bandwidth high-precision applications. It uses a coarse-conversion 5-bit asynchronous self-timed SAR ADC combined with a fine-conversion second-order delta-sigma modulator to efficiently obtain a high signal-to-noise distortion ratio (SNDR). An integrator circuit using a high-gain dynamic amplifier is proposed to achieve higher SNDR. The dynamic amplifier uses a switched tail current source to operate periodically, simplifying the common-mode feedback circuit, reducing unnecessary static current, and improving the PVT robustness. Dynamic error correction techniques, such as redundancy, chopping, and dynamic element matching (DEM) are used to achieve low offset and high linearity. And a 2-bit asynchronous SAR quantizer with an embedded feed-forward adder is used in the second-order delta-sigma modulator to reduce the quantization noise caused by redundancy, and further achieve higher energy efficiency. Simulation results show that the ADC achieves a peak SNDR of 121.1 dB in a 390 Hz bandwidth at a 200 kHz sampling clock while consuming only 170 μW from a 2.5 V supply and the core area is 0.55 mm2. This results in a Schreier figure of merit (FoM) of 184.7 dB.

周波数同期型発振回路の時間分解能を利用した1.2 v, 15.8ビット容量-デジタル変換ic

Abstract: In this paper, we propose a new architecture for Capacitance-to-Digital convertor. We clarified the configuration that utilizes the time resolution of the frequency-Locked-Loop oscillator using a switched capacitor that enables stable operation, and integrated the circuit using 0.18µm standard CMOS technology. As a result, a power supply voltage of 1.2V, a capacitance resolution of 15aF, ENOB of 15.8bit, high resolution, and wide dynamic range conversion characteristics were achieved.

A 7.9-ENOB 1. 5GS/s Common-Mode and Temperature Insensitive Pipelined-SAR ADC with an On-Chip Temperature-Sensor-Based Stage-Gain Compensation

Abstract: Pipelined-SAR ADCs utilizing a dynamic amplifier (DA) as a residue amplifier (RA) has become popular due to its potential to achieve both high speed and excellent power efficiency. A notable challenge though is that the gain of the DA is sensitive to process and temperature as well as to input common-mode voltage ($\mathrm{V}_{\mathrm{l}\mathrm{N}\mathrm{C}\mathrm{M}}$). Although there are several previous works aiming at compensating the temperature sensitivity of the DA [1], the lack of regulating DA’s output common-mode voltage (VOUTCM) makes them hard to be applied to pipelined ADCs having more than two stages. This is because the variation of VOUTCM directly leads to $\mathrm{V}_{\mathrm{l}\mathrm{N}\mathrm{C}\mathrm{M}}$ variation of the DA in the subsequent stage, significantly impacting the gain of the DA. Also, due to DA’s high |$\Delta \mathrm{v}_{0\cup \mathrm{T}\mathrm{C}\mathrm{M}/\Delta \mathrm{V}_{\mathrm{l}\mathrm{N}\mathrm{C}\mathrm{M}}|}$, small $\mathrm{V}_{\mathrm{l}\mathrm{N}\mathrm{C}\mathrm{M}}$ variation at the ADC input propagates through the stages, potentially driving the DA in the later stages out of acceptable $\mathrm{V}_{\mathrm{l}\mathrm{N}\mathrm{C}\mathrm{M}}$ range. This work presents a promising solution to such challenges with a new reset scheme and an on-chip temperature-sensor-based gain compensation scheme for the DA. The measured results validate that the ADC with proposed techniques operates reliably over temperature variation of 100°C and $\mathrm{V}_{\mathrm{l}\mathrm{N}\mathrm{C}\mathrm{M}}$ variation of 112mV.

Low-Complexity RMS-enhanced Digital Pre-emphasis under Limited Transmitter Power and ENoB

Abstract: We optimize digital pre-emphasis for narrow optical filtering using the balance among electrical RMS, equalization-enhanced noise and quantization, and experimentally show a low-complexity cutoff approach to enhance SNR in strong pre-emphasis.

Demodulation Performance Comparison of High-Speed Coherent Nyquist Pulse Signal with Analog and Digital Demultiplexing Schemes

Abstract: We compare the demodulation performance of an analog OTDM demultiplexing scheme and digitized OTDM demultiplexing with an ultrahigh-speed digital signal processor in a single-channel OTDM coherent Nyquist pulse transmission. We evaluated the demodulation performance for 40, 80, and 160 Gbaud OTDM signals with a baseline rate of 10 Gbaud. As a result, we clarified that the analog scheme performs significantly better since the bandwidth for handling the demultiplexed signal is as narrow as 10 GHz regardless of the symbol rate. This enables us to use a low-speed A/D converter (ADC) with a large effective number of bits (ENOB). On the other hand, in the digital scheme, the higher the symbol rate becomes, the more bandwidth the receiver requires. Therefore, it is necessary to use an ultrahigh-speed ADC with a low ENOB for a 160 Gbaud signal. We measured the ENOB of the ultrahigh-speed ADC used in the digital scheme and showed that the measured ENOB was approximately 1.5 bits lower than that of the low-speed ADC used in the analog scheme. This 1.5-bit decrease causes a large degradation in the demodulation performance obtained with the digital demultiplexing scheme.

A 0.55V 10-Bit 100-MS/s SAR ADC With 3.6-fJ/Conversion-Step in 28nm CMOS for RF Receivers

Abstract: This brief proposes a low voltage ultra-low power 10-bit 100-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). To overcome the performance degradation due to the signal-related current fluctuation under lower supply voltage, an adaptive-biasing comparator with current self-compensation (CSC) technique is proposed to obtain a constant working current, reducing the minimum supply voltage from 0.7V in conventional ADCs to 0.55V. Since full-scale range shrinks with the supply voltage, voltage undershoot in power rail caused by capacitor digital-to-analog converter (C-DAC) deteriorates effective-number-of-bits (ENOB). Conventional solutions involve enhanced regulators and large decoupling capacitors, which cost remarkable power dissipation and large chip area. This brief presents a pulse-injection undershoot compensation technique which reduces the DAC-related supply fluctuation from a typical 15mV to 1.8mV, and improves the ENOB by 0.4 bit. The prototype was fabricated in TSMC 28nm HPC CMOS technology. The proposed SAR ADC achieves an SNDR of 54.7dB and an SFDR of 68dB with the power consumption of 0.16mW under 0.55V supply voltage, a figure of merit (FoM) of 3.6-fJ/conversion-step is achieved. The chip area of the ADC core is $130\mu m \times 225\mu m$ .

Research on a high-precision SAR ADC based on non-binary redundancy structure

Abstract: SAR ADC has the characteristics of simple structure, low power consumption, high energy efficiency and good process compatibility. Nowadays, more and more scenarios have higher requirements for the accuracy of SAR ADC. A 14bits SAR ADC with calibration function was designed based on a 0.18μm CMOS process. Design a DAC with a segmented non-binary redundant architecture. Segmented DACs effectively reduce area overhead, while non-binary weighting reduces the effect of capacitor mismatched accuracy, thereby improving ADC accuracy. The simulation condition is that the sampling rate is 1MSPS, and the simulation results show that: Using this calibrated SAR structure, the ENOB is 13.34bits, the SNR is 74.03dB, the SFDR is 81.36dB, and the THD is -79.20dB.

A capacitor mismatch calibration scheme for SAR ADC based on genetic algorithm

Abstract: Capacitor mismatch problem due to process variation causes weight error, which deteriorates the linearity of SAR ADC. In this paper, a novel calibration scheme based on genetic algorithm(GA) combined with a radix-less-than-2 SAR ADC is proposed to extract the weight error caused by capacitor mismatch. This is a foreground calibration scheme and no extra injections are added. The proposed GA-based calibration scheme is simulated based on 40 nm CMOS technology. After calibration, ENOB increases from 10.19 bits to 11.46 bits, INL changes from +2.22/−2.12 LSB to +0.81/−0.80 LSB, and DNL changes from +1.79/−1.00 LSB to +0.99/−1.00LSB. As can be seen from the simulation results, the proposed calibration scheme can effectively improve the linearity deterioration caused by capacitor mismatch.

Analysis of SAR ADC Performance Enhancement utilizing Stochastic Resonance

Abstract: Stochastic resonance (SR) is a phenomenon where the noise of a certain intensity helps to improve the signal-to-noise ratio (SNR) of nonlinear systems. This brief applies this concept to a successive approximation register (SAR) analog-to-digital converter (ADC) to enhance its performance. To improve the effective number of bits of the SAR ADC, some additional comparisons are repeated after the normal binary search. The theoretical analysis of the performance enhancement based on the statistical information provides the optimal number of additional comparisons in terms of the ADC figure-of-merit (FoM). As this scheme allows the use of a high-input-referred-noise but low-power comparator in the SAR ADC, the total power consumption can be reduced even with the additional comparisons.