Showing papers on "Electronic circuit simulation published in 1991"

An experimentally verified IGBT model implemented in the Saber circuit simulator

Abstract: A physics-based insulated gate bipolar transistor (IGBT) model is implemented in the general-purpose circuit simulator Saber. The IGBT model includes all of the physical effects that have been shown to be important for describing IGBTs, and the model is valid for general external circuit conditions. The Saber IGBT model is evaluated for the range of static and dynamic conditions in which the device is intended to be operated, and the simulations compare well with experimental results for all of the conditions studied. >

Josephson junctions in SPICE3

Abstract: SPICE3 is the most recent version of the circuit simulator SPICE from the University of California, Berkeley. Unlike its predecessors, SPICE3 is written in the C programming language, and is designed for interactive use under a modern multitasking operating system. The Berkeley distribution of SPICE3 lacks support for Josephson junctions. As a consequence, the author has developed a customized version of SPICE3b.1 which incorporates a Josephson junction model. The model supports control current modulation, as well as fifth-order polynomial description of the quasiparticle current suitable for NbN junctions. In addition, a margin analysis command has been added, allowing operating ranges to be determined for an arbitrary circuit with a minimum of simulation. Further enhancements include the addition of a second graphics post-processor with new features and display, as well as debugging and streamlining of the original code. The program is currently configured to run on an IBM/Intel 386 compatible computer with Weitek coprocessor, under DOS extender software. The modifications to SPICE3 are described, and some of the issues involved in simulating Josephson circuits are also addressed. The features and philosophy of the SPICE3 program are discussed, and sample results presented.

MOSFET substrate current model for circuit simulation

Abstract: A simple, accurate MOSFET substrate current model suitable for a circuit simulator is presented. The effect of substrate bias on substrate current is modeled without introducing additional parameters. The accuracy of this model is demonstrated by its ability to fit the experimental data for both standard and LDD devices with average errors of less than 6%. The new model is compared with the substrate current models reported in the literature. In addition, the temperature dependence of the substrate current in the range of 0-120 degrees C is also modeled. The new model has been implemented in a circuit-level hot-electron reliability simulator, and the results obtained from simulation of an inverter circuit are presented. >

Simulation of arbitrary transmission line networks with nonlinear terminations

Abstract: The transient response of a high-speed digital circuit is determined by the interaction of a lossy distributed transmission line network and lumped nonlinear circuits. A robust and accurate method for the analysis of such a system is reported, and its implementation in an analog circuit simulator is discussed. The method uses a convolution technique and a time-domain impulse response to perform a transient simulation of a transmission line network. The time-domain impulse response is derived using a Fourier transform of modified frequency-domain scattering parameters. Implementation of the technique is verified by comparison with measured results. >

Measurement-based system for modeling and simulation of active semiconductor devices over an extended operating frequency range

Abstract: A modeling system for active semiconductor devices, such as gallium arsenide field effect transistors, for nonlinear (e.g., harmonic balance) circuit simulation. The model enables fast and unambiguous construction (model generation) by explicit calculations applied to raw device response data obtained using an adaptive, automated data acquisition system employed to characterize the device. The automated data acquisition system obtains the data adaptively, taking more data where nonlinearities are most severe and within a calculated, safe operating range of the device. The system converts conventional d.c. and S-parameter data directly into a detailed, device-specific, large-signal model. The system is extremely fast and replaces the need for conventional parameter extraction based on circuit simulation and optimization techniques. The measurement-based model improves large-signal simulation accuracy over an extended operating frequency range, because the model nonlinearities are explicitly constructed from device response data. The model is non quasi-static in that it accounts for frequency dispersion effects. Scaling rules allow devices of various geometries to be simulated from measurements on a single device. Therefore, the model is general, being technology and process independent in that the same calculation procedure applies to any device for which the equivalent circuit is valid. The model implementation in the automated data acquisition system, model generator, and harmonic balance (nonlinear) circuit simulator provides an efficient, practical system for state-of-the-art nonlinear circuit design.

Delay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations

Abstract: A method for analysis of VLSI interconnects that contain both lossy coupled transmission lines and nonlinear components is presented. An equivalent time-domain macromodel is derived for the linear subnetworks that contain lossy coupled transmission lines. The macromodel takes the form of a set of ordinary differential equations. The method takes full advantages of the asymptotic waveform evaluation (AWE) technique, which offers two to three orders of magnitude speed-up relative to other methods with comparable accuracy. In addition, it does not require explicit evaluation of the dominant poles of the network. The proposed technique can be easily implemented within the framework of an existing conventional circuit simulator such as SPICE. >

Retarded models for PC board interconnects-or how the speed of light affects your SPICE circuit simulation

Abstract: It is shown that retardation effects, due to the finite speed of electromagnetic interactions, play a significant role for PC-board interconnects. It is demonstrated that in some cases errors of more than an order of magnitude result in some frequency components when retardation is neglected. Extensions to a circuit simulator are introduced that make it possible to do retarded circuit simulation. Specifically, an algorithm to extend SPICE-level simulators to include retardation is presented. Comparisons with analytical equations, the method of moments, and with measurements show good agreement. >

Exact simulation of feedback circuit parameters

Abstract: Techniques for finding the important parameters of a single-loop feedback circuit at the closed-loop DC operating point are presented. The main advantage of these techniques is that they allow exact computer simulation of feedback parameters with a circuit simulator such as SPICE. Maintaining the closed-loop DC bias point in all test circuits makes it possible for the circuit simulator to compute the small-signal models for all nonlinear elements correctly. The methods presented for simulating loop transmission are particularly valuable since they can be used to accurately determine gain and phase margin using frequency-domain analysis, which is faster and more efficient than simulating step response via transient analysis. The equations behind the two methods for calculating loop transmission are presented as background. Examples are included to demonstrate the techniques. >

DC Analysis of Non-Linear Circuits using Solution Tracing Circuits

Abstract: A practical method of analyzing multi-valued DC characteristic curves of non-linear circuits is proposed. In this method, the characteristic curves can easily be traced by executing TRAN analysis with a conventional general-purpose circuit simulator. Some numerical examples including a bipolar analog 1C are also presented to demonstrate the effectiveness of this method.

Simulating EM fields

Abstract: Software tools for simulating and analyzing electromagnetic (EM) fields are described, with particular reference to integrated circuits (ICs). The use of a three-tiered approach for large-scale design is discussed, and a different tool is needed at each level. The most prudent approach today is to solve small pieces of a large problem and use a linear circuit simulator to combine the S-parameter files from the subnetworks. Several such simulators are described. A table of representative software packages is included. >

Improving DC convergence in a circuit simulator using a homotopy method

Abstract: To help resolve DC convergence difficulties in a circuit simulator, the authors constructed a homotopy suitable for solving equations describing transistor circuits. The authors describe its implementation in the ADVICE circuit simulator using a software package that implements a globally convergent homotopy algorithm. Homotopy methods proved robust, accurate, and capable of finding multiple operating points. The authors give simulation examples of various bipolar and MOS transistor circuits that could not be simulated using existing techniques, while the solution was successfully obtained using homotopy methods. >

Numerical device modeling for electronic circuit simulation

Abstract: Numerical MOSFET modeling based on multidimensional Bernstein interpolation is presented as a means to improve simulation efficiency. Device operating-point information is extracted from prestored table values using functional reconstruction during transient simulation. The formulation of the numerical model conforms to the requirements of electronic circuit simulators which use the Newtonian-Raphson algorithm to solve the algebraic differential circuit equations. This Bernstein approximation technique is extended to multidimension variation diminishing interpolation and applied to DC current and intrinsic charge modeling of MOSFETs. The implementation of the numerical model is described, and experimental results based on the simulation of benchmark circuits are provided. >

An analytical IGBT model for power circuit simulation

Abstract: On the basis of the physical picture obtained by a detailed two-dimensional numerical simulation, an analytical CAD (computer-aided design) model for an IGBT (insulated-gate bipolar transistor) is developed which has sufficient flexibility to account for the unique characteristics of IGBT operation, while still retaining a mathematically simple form with readily extractable model parameters. The static model has been implemented in the circuit simulator SPICE. A systematic method of DC model parameter extraction is developed based on the parameter optimization program TOPEX. A set of model parameters extracted for a n-channel 600-V, symmetric IGBT is shown. Good agreement has been obtained between the simulation results and measurements. >

A qualitative circuit simulator

Abstract: The work described here is part of a larger project which is investigating various issues related to diagnosis and failure prediction in the context of automotive manufacturing. In particular, the goal is to produce prototype intelligent tools which will assist in the analysis of potential faults and hazard situations in evolving electrical circuit designs. The paper reports on the design and implementation of a qualitative electrical circuit simulator that can effectively model the structure and behaviour of systems under analysis. The simulator assigns labels to open and short circuit branches, finds current paths and determines directions of flow. >

Transient sensitivity computation and applications

Abstract: Sensitivity information is extremely useful in assessing and improving the performance and robustness of VLSI designs. However, there are inherent limitations that make the computation of transient, or time domain, sensitivities prohibitively expensive in a circuit simulation environment. This work exploits the simplified models and the event-driven nature of piecewise approximate circuit simulation to provide a highly efficient transient sensitivity computation, which has been applied successfully to industrial circuits of up to 1500 MOSFETs. Applications that have been considered previously to be prohibitively expensive in circuit design, verification, and optimization could benefit from such a sensitivity capability. In this work, the overall efficiency of the prototype piecewise approximate circuit simulator SPECS and its transient sensitivity computation has been exploited in two potential applications: model simplification/simulation validation and circuit optimization. Results indicate that SPECS coupled with its sensitivity extension can provide a unique capability to improve simulation efficiency by simplifying device and circuit models, and to validate the corresponding simulation results. In addition, SPECS and the sensitivity computation can also be employed for practical optimization of reasonably large integrated circuits as well as for assessing the robustness of designs with respect to unwanted parasitics and second order effects.

Hierarchical simulation of hot-carrier induced damages in VLSI circuits

Abstract: A hierarchical simulation tool is presented for estimating the hot-carrier-induced degradation of nMOS transistor characteristics and circuit performance in large-scale circuits. This information can be used both for understanding the circuit-level dynamics of the degradation mechanisms and as a design aid for improving the long-term reliability through design modifications. A two-tier hierarchical approach is adopted for hot-carrier reliability simulation of large-scale circuits. First, the circuit is simulated using a fast simulator to detect subcircuits likely to cause reliability problems. Then, detailed simulation is performed on the suspected subcircuits. The fast simulation is performed using the mixed-mode simulator iDSIM2, whereas the circuit simulator iSMILE is used for the detailed simulation. >

High speed digital system simulation using frequency dependent transmission line network modeling

Abstract: A robust and accurate method for the analysis of high-speed digital circuits with a lossy, frequency-dependent transmission line network is presented. Implementation in an analog circuit simulator, using convolution and time-domain scattering parameters, in combination with a linear microwave circuit simulator is discussed. >

An efficient symbolic approach to time delay optimization of CMOS circuits

Abstract: An approach to automatic generation of symbolic models relating a digital cell delay to CMOS transistor dimensions is proposed and used for deterministic and statistical delay optimization in combinational CMOS VLSI circuits. The models used provide about 5% accuracy with respect to the SPICE-3 circuit simulator, but are up to 5 to 6 orders of magnitude faster. A first order statistical device model is introduced. Examples of optimization of several VLSI circuits are shown, the largest being composed of about 1200 transistors, with 380 gate widths and 10 different active delay paths optimized in 308 CPU seconds. A generic optimization system, able to perform the relevant deterministic and statistical optimization tasks, is described. >

A pragmatic approach to integrated process/device/circuit simulation for IC technology development

Abstract: A novel approach to integrated process/device/circuit simulation is proposed. It makes pragmatic, computationally efficient IC technology CAD (computer-aided design) possible at the mixed-mode device/circuit level. The approach is demonstrated with a simulation system for advanced bipolar technologies. This system comprises the process simulator SUPREM-3 integrated with the seminumerical mixed-mode device/circuit simulator MMSPICE by a program called SUMM. The integration is characterized by the unique evaluation of the physical (structure-dependent) parameters for the MMSPICE BJT (bipolar junction transistor) model from a one-dimensional doping profile generated by SUPREM-3 (without any optimization-based extraction). The predictive capability of the SUMM/MMSPICE integrated system is verified by measurements and purely numerical simulations with PISCES-II. The utility of the system in IC technology development is exemplified by simulations showing the effects of variations in an advanced bipolar process flow on the performance of an ECL circuit. >

A new MOS circuit primitive for fast timing simulations

Abstract: A new MOS circuit primitive, of which an inverter is a special case, is presented. The proposed MOS circuit primitive is shown to be more suitable for switch level and fast timing simulations than the commonly used inverter. The approach for obtaining the exact analytic transient solution of this general MOS primitive for piecewise-linear inputs is also presented. For circuit simulation of medium-size digital circuits containing a few hundred transistors, the application of this primitive along with its analytic solution has resulted in two to three orders of speed improvement over the conventional circuit simulator. >

Transient three-dimensional mixed-level circuit and device simulation: algorithms and applications

Abstract: The authors describe algorithms for transient mixed-level circuit and device simulation using a two-carrier three-dimensional device simulator SIERRA and the circuit simulator SPICE3. It is pointed out that algorithms well suited to 2D mixed-level circuit and device simulation cannot be successfully used. The memory and CPU time requirements in 3D device simulation necessitate it the use of iterative solution techniques at the device level, which impose an additional constraint in developing efficient algorithms. Two node tearing schemes are shown to be the most promising schemes for coupling the circuit and device simulators. An application of 3D mixed-level simulation to the study of single-event upset of SRAM cells is presented. >

Mozart-MM: A mixed-mode and multi-level simulation system

Abstract: The authors describe the Mozart-mixed mode (MM) simulation system which was formed by a tight coupling of the Mozart multi-level simulator and the Eldo analog simulator. Mozart-MM spans all the digital levels from behavioral to pseudo-electrical as well as the analog circuit and behavioral levels. This work required the development of a new algorithm to couple a digital simulator with discrete time together with a circuit simulator with adaptable time step. The full Mozart interactivity has been extended to Mozart-MM allowing the user to have direct control of the simulation experiment, including the possibility to conditionally execute commands. New techniques for netlisting, X handling and for the verification of the interface unidirectionally assumption are also presented. The tool has been tested extensively and the results presented demonstrate its performance. >

HIGH PERFORMANCE PIN ELECTRONICS EMPLOYING GaAs IC AND HYBRID CIRCUIT PACKAGING TECHNOLOGY

Abstract: This paper describes the latest generation of pin electronics developed for a high-speed verification ATE system. The pin electronics sub-system provides a driverireceiver with outstanding bandwidth in addition to per-pin current loading and per-pin parametrics. A f.11 custom GaAs IC provides the major features and advanced performance of the driver, receiver, and current load. The combined modules use only 2.5 square inches of circuit board area per tester channel. This paper details the circuit design and measured perfor,mance of the GaAs IC and the three hybrid multichip rzwdules that complete the pin electronics Bnctions.

Smart-power devices seek wiser CAE tools

Abstract: The difficulties in developing generalized computer design tools for smart-power semiconductor electronics, a highly specialized field requiring a mix of analog and digital integrated-circuit design, unique semiconductor-device-fabrication technology, and knowledge of application-specific power systems, are examined. These include the problem of dealing with the double-diffused MOS (DMOS) transistor, as well as the simulation of trench refill processes, 2D oxidation phenomena and their stress-induced effects on avalanche breakdown, and the 3D diffusion of the spherical junctions encountered in high-voltage termination. The complexities associated with 2D simulations are discussed in some detail. Dealing with asymmetric devices and with structures consisting of circles, arcs, and 45 degrees angles is also considered. >

Parameter estimation algorithm for performance fine tuning of switching DC power supplies

Abstract: A parameter estimation algorithm to aid power converter designers in fine-tuning the performance of switching DC power supplies is described. This algorithm identifies the optimal parameter values which satisfy the design specifications. The estimation algorithm is incorporated with a fast time-domain circuit simulator to form a user-friendly design environment. Numerical results are provided. The estimation algorithm is general and can be applied to other types of converter design. >

Enhanced circuit simulation: Expectations, problems, implementation, and integration

Abstract: During the late 60s and throughout the 70s, the field of circuit simulation has advanced in step with the increase in the use of analog integrated circuits. The general purpose circuit simulator SPICE was released in this period. During the 80s, in addition to pure analog circuits, digital and mixed analog-digital VLSI circuits also saw dramatic increases in usage. In this paper, we will discuss the roles that manufacturers are coming to expect that circuit analysis techniques will play in the development of VLSI circuits. Specifically, we will consider the limitations that general purpose simulators like SPICE have and enhancements needed in the future. We will consider these limitations by specifically considering problem analysis methods developed for each limitation. Finally, we present ideas for future work.

Switched capacitor circuit and switched capacitor filter circuit

Abstract: PURPOSE:To obtain a desired characteristic just after starting an operation and further to shorten design according to simulation by providing an analog switch for initialization to short-circuit the both ends of a capacitive element corresponding to a clock for initialization. CONSTITUTION:In the state of closing an analog switch 38, the both ends of a capacitive element 18 are short-circuited. For example, when a clock phia is made H by turning a power source on, therefore, charges stored in the capacitive element 18 are discharged through the analog switch 38 and the charge of the capacitive element 18 is initially set to zero. Afterwards, clocks phi1 and phi2 are made active and H at prescribed timing t2 and t3, etc. Therefore, the desired characteristic can be obtained from the beginning of the operation by setting the initial charge of the capacitive element 18. As a result, a dynamic range can be secured and offset can be reduced. Even when the design in executed by the simulation, the simulation is enabled in a much shorter time because it is not necessary to idly feed a circuit simulator, and inspection ability is improved.