Showing papers on "Fault detection and isolation published in 1989"

Failure detection and identification

Abstract: Using the geometric concept of an unobservability subspace, a solution is given to the problem of detecting and identifying control system component failures in linear, time-invariant systems. Conditions are developed for the existence of a causal, linear, time-invariant processor that can detect and uniquely identify a component failure, first for the case where components can fail simultaneously, and then for the case where they fail only one at a time. Explicit design algorithms are provided when these conditions are satisfied. In addition to time-domain solvability conditions, frequency-domain interpretations of the results are given, and connections are drawn with results already available in the literature. >

Formal methods for protocol testing: a detailed study

Abstract: The authors present a detailed study of four formal methods (T-, U-, D-, and W-methods) for generating test sequences for protocols. Applications of these methods to the NBS Class 4 Transport Protocol are discussed. An estimation of fault coverage of four protocol-test-sequence generation techniques using Monte Carlo simulation is also presented. The ability of a test sequence to decide whether a protocol implementation conforms to its specification heavily relies on the range of faults that it can capture. Conformance is defined at two levels, namely, weak and strong conformance. This study shows that a test sequence produced by T-method has a poor fault detection capability, whereas test sequences produced by U-, D-, and W-methods have comparable (superior to that for T-method) fault coverage on several classes of randomly generated machines used in this study. Also, some problems with a straightforward application of the four protocol-test-sequence generation methods to real-world communication protocols are pointed out. >

Evaluation of error detection schemes using fault injection by heavy-ion radiation

Abstract: Several concurrent error detection schemes suitable for a watch-dog processor were evaluated by fault injection. Soft errors were induced into a MC6809E microprocessor by heavy-ion radiation from a Californium-252 source. Recordings of error behavior were used to characterize the errors as well as to determine coverage and latency for the various error detection schemes. The error recordings were used as input to programs that simulate the error detection schemes. The schemes evaluated detected up to 79% of all errors within 85 bus cycles. Fifty-eight percent of the errors caused execution to diverge permanently from the correct program. The best schemes detected 99% of these errors. Eighteen percent of the errors affected only data, and the coverage of these errors was at most 38%. >

Fault detection and management system for fault-tolerant switched reluctance motor drives

Abstract: The unique characteristics that promote the switched reluctance motor (SRM) for fault tolerance capability, i.e. its ability to continue operation despite faulted motor windings or inverter circuitry, are discussed. It is shown that the magnetic independence of the motor phases and the circuit independence of the inverter phases permit the SRM drive to continue operation with one or more phases disabled. Winding fault detectors indicate the existence of faulted motor windings, and control circuitry acts to block the gating signals to the semiconductor power switches of the affected phase, thus removing excitation from the faulted winding and halting damaging effects that can result from the continued excitation of a faulted winding. The drive an continue operation without the faulted phase. >

Auxiliary Signal Design in Fault Detection and Diagnosis

Abstract: Preliminaries.- Sequential probability ratio test.- Auxiliary signals for improving fault detection.- Extension to multiple hypothesis testing.- Modelling and identification of the chemical process.- Fault detection and diagnosis in the chemical process.- Conclusions and further research.

On-Line Detection of Localized Defects in Bearings by Pattern Recognition Analysis

Abstract: A pattern recognition analysis scheme was developed for investigating vibration signals of bearings. Two normalized and dimensionless features are extracted by short-time signal processing techniques. Employing these two features, two linear discriminant functions have been established to detect defects on the outer race and rollers of bearings, respectively. Results of fault detection/diagnosis, based on the experimental data of imposed bearing defects, indicated the technique to be 14 percent better in the rate of success for the detection of defects than the best among the state-of-the-art

Synthesis of pseudo-random pattern testable designs

Abstract: A method of synthesizing scan designs that are testable with pseudorandom patterns is presented. The logic is first simplified by various transformations in a logic synthesis system. A fault simulator is then used to guide the placement of control points and observation points. In order to reduce the overhead, control points are shared when possible and a condensation network is used with the observation points. Experimental results which indicate that pseudorandom testability can be achieved with small area overheads using simple techniques are presented. >

Parallel Pattern Fault Simulation of Path Delay Faults

Abstract: This paper presents an accelerated fault simulation approach for path delay faults. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and non-robust detection of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.

Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation

Abstract: The COSMOS symbolic fault simulator generates test sets for combinational and sequential MOS circuits represented at the switch level. All aspects of switch-level networks including bidirectional transistors, stored charge, different signal strengths, and indeterminate (X) logic values are captured. To generate tests for a circuit, the program derives Boolean functions representing the behavior of the good and faulty circuits over a sequence of symbolic input patterns. It then determines a set of assignments to the input variables that will detect all faults. Symbolic simulation provides a natural framework for the user to supply an overall test strategy, letting the program determine the detailed conditions to detect a set of faults. Symbolic preprocessing of switch-level networks, combined with efficient Boolean manipulation makes this approach feasible.

Local Sensor Validation

Abstract: Current approaches to plant fault detection require an overall process model. This paper argues that a hierarchical scheme is more efficient in which the lowest level concentrates on validating the signals transmitted by individual sensors. Signals are described in terms of standard time-series models. A fault is defined by the signal's deviation from its expected behaviour and various signal processing techniques are described which detect these aberrations.

Delay test generation for synchronous sequential circuits

Abstract: The author presents a method for generating test sequences to detect delay faults in sequential circuits using the stuck-at-fault sequential test generator STALLION. The method is complete in that it will generate a delay test sequence for a targeted fault given sufficient CPU time, if such a sequence exists. Faults for which no delay test sequence exists are termed sequentially delay redundant. The author describes means of eliminating sequential delay redundancies in logic circuits. He presents a partial-scan methodology for enhancing the testability of difficult-to-test or untestable sequential circuits, wherein a small number of flip-flops are selected and made controllable/observable. The selection process guarantees the elimination of all sequential delay redundancies. It is shown that an intimate relationship exists between state assignment and delay testability of a sequential machine. A state assignment algorithm for the synthesis of sequential machines with maximal delay fault testability is described. Preliminary experimental results using the test generation, partial-scan, and synthesis algorithms are presented. >

Power cable arcing fault detection system

Abstract: A system for detecting an arcing fault in a telephone central office DC power distribution conductor repeatedly measures the current flow in the distribution line, as with an inductive coupling, and derives a Fourier transform analysis spectrum from such measurements. The power values at intervals across the frequency spectrum are compared with recorded threshold template values encompassing the spectrum typical of an arcing event and an alarm condition is established when such threshold levels are exceeded.

Classification of faults and switching events by inductive reasoning and expert system methodology

Abstract: Under certain conditions, one electrical parameter (independent variable) is not enough to detect high-impedance faults on certain surface conditions. These faults do not draw sufficient current for detection and may draw less current than similar faults on other soil surfaces. Moreover, because every electrical detection parameter displays characteristics of randomness, it is difficult to assign a probability that a given event is a high-impedance fault, rather than a switching event. It has been shown that detection by induction laws can improve the classification of faults and switching events. The second and third laws of induction are utilized with a minimum entropy method. Setting detection threshold values using induction methods is also proposed. The methods presented are taken from ongoing research in high-impedance fault detection. While the techniques have not been reduced to practice or field-tested, they hold promise for future improvements in the relaying of high-impedance faults. >

Fault detection in combinational networks by Reed-Muller transforms

Abstract: A new approach for fault detection in combinational networks based on Reed-Muller (RM) transforms is presented. An upper bound on the number of RM spectral coefficients required to be verified for detection of multiple stuck-at-faults and single bridging faults at the input lines of an n-input network is shown to be n. The time complexity (time required to test a network) for detection of multiple terminal faults and the storage required for storing the test are determined. An upper bound is found for the minimum number of test patterns required to detect a fault. The authors present standard tests based on this result, with a simple test generation procedure and upper bounds on minimal numbers of test patterns. >

Built-in-test by signature inspection (bitsi)

Abstract: A system and method for fault detection for electronic circuits. A stimulus generator sends a signal to the input of the circuit under test. Signature inspection logic compares the resultant signal from test nodes on the circuit to an expected signal. If the signals do not match, the signature inspection logic sends a signal to the control logic for indication of fault detection in the circuit. A data input multiplexer between the test nodes of the circuit under test and the signature inspection logic can provide for identification of the specific node at fault by the signature inspection logic. Control logic responsive to the signature inspection logic conveys information about fault detection for use in determining the condition of the circuit. When used in conjunction with a system test controller, the built-in test by signature inspection system and method can be used to poll a plurality of circuits automatically and continuous for faults and record the results of such polling in the system test controller.

Fault detection via optimally robust detection filters

Abstract: An approach is presented for using optimally robust detection filters to generate analytic redundancy. By introducing an appropriate criterion the design of the filter is formulated as an optimization problem. Its solution shows that the optimally robust detection filter consists of a bandpass filter and a linear system which is obtained by solving a general eigenvalue problem. The algorithm for designing this filter is therefore computationally simple and systematic. Investigations on the physical core of the fault detection procedure are carried out. It is shown that the quality of the fault detection is dependent on the coupling strength of the faults with respect to the system output. It is demonstrated that the optimal detection filter presented is a generalization of the detection filter of R.V. Beard (1971) and H.L. Jones (1973). >

CrossCheck: A Cell Based VLSI Testability Solution

Abstract: A new testability solution is proposed in which externally accessible test points are pre-designed into cells that comprise the VLSI designs. The test points are accessed through an on-chip grid of orthogonal probe and sense lines. The resultant VLSI design consists of a large number of test points through which test signals on every cell on the IC can be measured or modified to a limited extent. The sizable number of test points improves the testability of the designs by a very large factor. Additionally, analog measurement and signal injection capabilities allow detection of practical CMOS fault modes such as opens, shorts, open or closed FETs and even noise margins. The large observability of CrossCheck based designs reduces the automatic test pattern generation problem to one of providing control only. Several ISCAS benchmark designs are analyzed using CrossCheck cell libraries and fault models. The results show that over 97 percent coverage of a broad range of fault modes, such as opens and shorts, can be obtained on VLSI CMOS designs without the need for large computing resources.

Perturbation techniques for detecting domain errors

Abstract: Perturbation testing is an approach to software testing which focuses on faults within arithmetic expressions appearing throughout a program. This approach is expanded to permit analysis of individual test points rather than entire paths, and to concentrate on domain errors. Faults are modeled as perturbing functions drawn from a vector space of potential faults and added to the correct form of an arithmetic expression. Sensitivity measures are derived which limit the possible size of those faults that would go undetected after the execution of a given test set. These measures open up an interesting view of testing, in which attempts are made to reduce the volume of possible faults which, were they present in the program being tested, would have escaped detection on all tests performed so far. The combination of these measures with standard optimization techniques yields a novel test-data-generation method called arithmetic fault detection. >

Spare capacity as a means of fault detection and diagnosis in multiprocessor systems

Abstract: A technique for detecting and diagnosing faults at the processor level in a multiprocessor system is described A process is assigned whenever possible to two processors: the processor to which it would normally be assigned (primarily) and an additional processor that would otherwise be idle (secondary) Two strategies are described and analyzed: one that is preemptive and another that is nonpreemptive It is shown that, for moderately loaded systems, a sufficient percentage of processes can be performed redundantly using the system's spare capacity to provide a basis for fault detection and diagnosis with virtually no degradation of response time A multiprocessor that uses the approach for detecting faults at the processor loads is described >

Rethinking the Taxonomy of Fault Detection Techniques

Abstract: The conventional classification of software fault detection techniques by their operational characteristics (static vs. dy- namic analysis) is inadequate as a basis for identifying useful relationships between techniques. A more useful distinction is between techniques which sample the space of possible ex- ecutions, and techniques which fold the space. The new dis- tinction provides better insight into the ways different tech- niques can interact, and is a necessary basis for considering hybrid fault detection techniques.

Fault diagnosis in analogue circuits using AI techniques

Abstract: The authors describe a technique for detecting and locating faults in analogue circuits by checking that the measurements are consistent with the circuit function. The unique representation used accommodates the imprecise nature of analogue circuits. A model of the circuit is formed from the constraints imposed by the behavior of the components and the interconnections. The values of parameters within the circuit are deduced by propagating the effects of measurements through this model. Faults are implied from the detection of inconsistencies and located by suspending constraints within the model. The method does not use fault simulation and is therefore applicable to any type of fault. It is able to detect performance variations, as well as catastrophic failures. Values are represented as ranges within which the true value lies. This overcomes the difficulty of representing the uncertainty inherent in any analogue design or measurements. The method has been successfully used to detect and locate a number of faults in several circuits. >

Fault detection method for central tire inflation system

Abstract: A self-diagnostic method for an on-board CTIS (10) for sensing system faults and/or vehicle conditions requiring system shut down. Includes a method for preventing operations of the CITS if the pressure in the air tank has not reached a desired minimum when the vehicle speed exceeds a reference speed for a preselected period of time.

Radio trunking fault detection system with power output monitoring and on-air monitoring

Abstract: A trunked radio frequency (RF) repeater system for public service trunking (PST) or the like includes a fault detection system having an RF output power monitoring, over-the-air RF monitoring and other repeater transceiver testing capabilities. An over-the-air monitor continually tests the digital signalling transmitted by different transceivers within the repeater system. The site controller automatically removes transceivers that test faulty, and does not permit tested faulty transceivers to go back on line until they have passed poll response, power output and RF digital signalling tests.

Unpredictable fault detection using adaptive inference testing techniques

Abstract: A method of using an adaptive inference system to detect and locate faults in an electrical or electronic device or assembly. A position-dependent, time-ordered test is performed upon the device or assembly to provide a comprehensive error analysis. The error analysis includes an array of error data and information that is time interdependent. Once fault data is stored in memory, a newly-detected fault can be compared with the stored faults. A relationship between the stored fault data and the detected fault is determined. The system indicates the cause of the detected fault to the operator based on stored fault data that is most probably related to the detected fault. Possibilites of faults within the device or assembly are then displayed. This system analysis and range of potential causes can be evaluated by an operator. In this manner, faults not having been contemplated by stored data and information in the adaptive inference system and not bearing a direct relationship to a problem being reviewed can be identified.

Fault detection in induction motors as a result of transient analysis

Abstract: A technique is being developed which will allow the detection and identification of specific faults within 3-phase induction motors during the starting transient. At present a very detailed and complex analysis is used to detect faults requiring the use of a mainframe computer. It is anticipated that once sufficient test data has been obtained this analysis will be dramatically reduced, allowing a stand alone instrument to be designed.

A Simplified Six-Waveform Type Method for Delay Fault Testing

Abstract: A new, simplified waveform method is presented for delay fault testing. The method enables accurate calculation of a delay fault detection threshold for definitely detectable faults, and a delay fault range for possibly detectable faults. The method is shown to correctly classify definitely detectable faults which are mis-classified by methods recently reported elsewhere [1] [2]. A quantitative delay fault model with variable fault size is used, and the effect of the delay fault is explicitly described by the new waveform method. The calculation of the detectable delay size threshold occurs in linear time for any definitely detectable fault.

Dynamic redundancy identification in automatic test generation

Abstract: Test generation for combinational circuits, an NP-complete problem, shows its worst-case behavior while trying to generate tests for redundant faults and failing after an exhaustive search. The performance of an automatic test generator can be significantly improved by identifying redundancy via simple techniques which do not involve a search. The authors present a technique to identify redundant faults. This technique works dynamically during test generation, but is not based on a search process. It relies on test-covering relations among faults, which allow identification of addition redundant faults after the test generator fails to generate a test for a target fault. This technique has been implemented in AT&T's Testpilot test generation system and has shown a reduction of up to 32% in the number of backtracks in test generation runs. >

High impedance fault detection for industrial power systems

Abstract: The authors describe the characteristics of high-impedance faults and the most effective techniques for detecting them. The benefits of high-impedance fault detection for industrial power systems are identified. It is shown that the most effective high-impedance-fault detection system incorporates several algorithms and monitors a number of parameters to ensure sensitivity and correct operation. Operating the detector in an alarm mode improves safety and fault location with minimal effect on service continuity. A valuable use for such a detector would be the identification of incipient faults, so that critical loads can be switched to another source before the fault becomes bolted and requires the circuit to be cleared. Using a detector in this way could save substantial down-time costs for critical processes. >