Showing papers on "FET amplifier published in 1999"

Dual-material gate (DMG) field effect transistor

Abstract: A generic new type of field effect transistor (FET), the dual material gate (DMG) FET, is proposed and demonstrated. The gate of the DMGFET consists of two laterally contacting materials with different work functions. This novel gate structure takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain (for n-channel FET, the opposite for p-channel FET), resulting in a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short-channel effects. Using the heterostructure FET as a vehicle, the principle, computer simulation results, design guidelines, processing, and characterization of the DMGFET are discussed in detail.

DRAM sense amplifier for low voltages

Abstract: Structures and methods for improving sense amplifier operation are provided. A first embodiment includes a sense amplifier having a pair of cross-coupled inverters. Each inverter includes a transistor of a first conductivity type and a pair of transistors of a second conductivity type which are coupled at a drain region and are coupled at a source region. The drain region for the pair of transistors is coupled to a drain region of the transistor of the first conductivity type. A pair of input transmission lines are included where each one of the pair of input transmission lines is coupled to a gate of a first one of the pair of transistors in each inverter. A pair of output transmission lines is included where each one of the pair of output transmission lines is coupled to the drain region of the pair of transistors and the drain region of the transistor of the first conductivity type in each inverter. High performance, wide bandwidth or very fast CMOS amplifiers are possible using the new circuit topology of the present invention. The new modified sense amplifier for low voltage DRAMs is as much as 100 times faster than a conventional voltage sense amplifier when low power supply voltages, e.g. Vdd less than 1.0 Volts, are utilized. In the novel sense amplifier, the bit line capacitance is separated from the output nodes of the sense amplifier.

Differential circuits employing forward body bias

Abstract: In some embodiments, the invention includes circuit having a differential amplifier and body bias control circuitry. The differential amplifier includes a differential pair of first and second FET transistors to at least partially control output voltage signals responsive to input voltage signals, the first and second FET transistors being configured to be matched and having a body. The body bias control circuitry provides a body bias voltage signal to the body to place the first and second FET transistors in a forward body bias condition. The differential amplifier and body bias circuitry may be used in a sense amplifier, comparator, voltage controlled oscillator, delay locked loop, and phase locked loop as well as other circuits.

Design of Class E power amplifier with nonlinear parasitic output capacitance

Abstract: The Class E amplifier exploits the output shunt capacitor for charge-storing during the operation cycle. The amplifier works even with a nonlinear output capacitor, but the required component values are different from the values resulting with the linear capacitor. In this paper the equations and component values are solved for the first time for a Class E amplifier having a nonlinear output capacitor with hyperabrupt junction voltage-capacitance characteristics. A hyperabrupt junction capacitor is present especially at the drain-to-bulk junction of practical MOS devices. The results of the analysis are presented in plots providing initial component values for MOS Class E power amplifier design. The procedure is validated with a design example of a single-stage 900 MHz MOS power amplifier operating from a 2-V supply voltage.

Transformer coupled stacked FET power amplifiers

Abstract: The development of high-power linear ultrahigh-frequency amplifiers is made difficult by the low impedance of the devices used in the output stage, which causes matching difficulties and high radio-frequency current levels. A stacked field-effect transistor (FET) configuration is shown to reduce these problems with its increased output impedance and lower current required for a given output power. A linear analysis of the stacked FET configuration is given. Two class A monolithic microwave integrated circuit amplifiers are developed and subjected to one- and two-tone tests to demonstrate the performance of the stacked FET as a power amplifier at 900 MHz.

High efficiency power amplifier having reduced output matching networks for use in portable devices

Abstract: A power amplifier includes a carrier amplifier path and a peaking amplifier path. The carrier amplifier path includes a carrier amplifier ( 208 ), and an impedance transforming network ( 214 ). The peaking amplifier path includes a peaking amplifier ( 210 ), an impedance transforming network ( 216 ), and a phase delay quarter wave element ( 226 ). The arrangement forms an inverted Doherty combiner where as the nominal impedance at a summing node ( 230 ) increases with increased conduction from the peaking amplifier, the load impedance at the output of the carrier amplifier decreases so as to maintain the carrier amplifier at a saturation point as the input signal ( 232 ) increases, and results in a reduction of the number of phase delay elements needed over a conventional Doherty approach. In a preferred embodiment the carrier and peaking amplifiers consist of cascaded stages, and are disposed on a common integrated circuit die ( 304 ). The impedance transforming networks and phase delay element are disposed on a common substrate ( 306 ), as is an input splitter network ( 308 ).

Rf power amplifier linearization using parallel rf power amplifiers having intermod-complementing predistortion paths

Abstract: An RF power amplifier linearization architecture has a pair of matched RF amplifiers, RF signal paths through which are intercoupled with a phase and amplitude measurement and predistortion mechanism. By selectively combining the RF output of a main path RF power amplifier with the RF input signal supplied to a parallel path RF power amplifier, the predistortion control mechanism of the invention predistorts the RF input signal applied to the parallel path amplifier, so that it includes the same modulated RF carrier component as that applied to the main path amplifier, as well as a complementary version of the intermodulation component of the output of the main path amplifier. The predistortion for each amplifier is controlled such that the resulting RF output signals produced by the matched amplifier pair will have the desired RF carrier modulation component but equal amplitude and phase-reversed intermodulation components. Combining these two matched amplifier outputs in a quadrature hybrid produces a composite signal, in which the desired amplified modulated RF carrier components produced by each matched amplifier constructively sum, while unwanted IMD components cancel.

High efficiency switched gain power amplifier

Abstract: A power amplifier circuit arrangement including a driver amplifier, a switch, an amplifier path having a band pass filter and a power amplifier, and a bypass path which bypasses the power amplifier when excess gain and output power are not needed. When an RF-analog signal from the driver amplifier is switched to the amplifier path, the signal is band-pass filtered and amplified. Then the signal is split into an in-phase and a quadrature signal. Either the in-phase or the quadrature signal is inverted and summed with the other of the in-phase or quadrature signal, and the summed signal is transmitted to an output port. When the RF-signal from the driver amplified is switched to the bypass path, the power amplifier is turned off and the bypass path directs the signal to the output of the power amplifier, which appears as a high impedance to the signal. The signal reflects off the power amplifier to the output port. This design preserves the benefits of bypassing the power amplifier by reducing the amount of switching loss introduced into the circuit.

Circuit and method for i/q modulation with independent, high efficiency amplitude modulation

Abstract: An RF amplifier includes a phase modulator developing a phase modulated RF input signal to be transmitted. A power amplifier receives the RF input signal and amplifies the RF input signal to develop an RF output signal. An amplifier control is operatively associated with the phase modulator and the power amplifier. The amplifier control includes a memory for storing correction information correlating desired amplitude of the RF output signal relative to actual amplifier amplitude, and a control varies power amplifier supply voltage responsive to the correction information to linearize amplitude modulation in the power amplifier.

Column amplifier for high fixed pattern noise reduction

Abstract: A column amplifier for high fixed pattern noise reduction. The column amplifier includes a switching capacitor amplifier, a sample and hold stage, and an output buffer. The switching capacitor amplifier receives signals from a bit line that is coupled to a column of active pixel sensors. The switching capacitor amplifier is capacitively coupled to the bit line from a column of active pixel sensors and is able to cancel the common mode offset in the bit line. The common mode can also be adjusted in the switching capacitor amplifier, such that the last stage of the column amplifier (e.g., the buffer stage) is not limited by the common mode level of the active pixel sensors. The switching capacitor amplifier includes an input capacitor and a feedback capacitor. The gain of the switching capacitor amplifier amplifies the pixel signals so that the fixed pattern noise introduced by stages after the switching capacitor amplifier will comprise a lower proportion of the total signal.

Control circuit for controlling a semi-conductor switch for selectively outputting an output voltage at two voltage levels

Abstract: A control circuit (1) for controlling a FET (2) for outputting a 3.3 volt or a regulated 1.5 volt output to an AGP bus on a PC motherboard in response to a TYPEDET signal being applied to a control terminal (3) of the control circuit (1) through an input (6) of a voltage divider circuit (8). The TYPEDET signal is received from a video card receiving slot and indicates the type of video card in the slot of the motherboard. An amplifier (20) outputs a control signal to the gate of the FET (2) for either disabling the FET (2), or enabling the FET (2) to output the 1.5 volt or the 3.3 volt outputs. A decoding circuit (30) decodes the state of the control terminal (3) and controls the amplifier (20) to disable the FET (2) during power up. When the TYPEDET signal of zero volts, the FET (2) is operated to output the 1.5 regulated voltage output. When the TYPEDET signal is floating, the FET (2) outputs the 3.3 source voltage. When the voltage on the control terminal (3) is not connected to the voltage divider circuit (8), the FET (2) is operated to output the 1.5 regulated voltage.

Power sensor for RF power amplifier

Abstract: A system for sensing RF amplifier output power includes an amplifier transistor and a sampling transistor that is physically smaller than the amplifier transistor. The sampling transistor is configured to sample the same RF input signal that is amplified by the amplifier transistor. A bias circuit associated with the transistors includes a selection of components based upon operating parameters as well as actual physical sizes of the transistors. The selection of component values in association with transistor sizes is used to enable generation of a current sensing signal that is proportional to the power level of the RF output signal generated by the amplifier transistor.

High efficiency feed-forward RF power amplifier with predistoration enchancement

Abstract: An RF power amplifier linearization architecture contains main and auxiliary path RF amplifiers. A distortion-inverting circuit (100) extracts the distortion component from the output signal of the main amplifier (A1) and combines it with a delayed sample of the RF input signal to drive an auxiliary path RF amplifier (A2), via a predistorter (293). An output quadrature hybrid (200) combines the output of the main and auxiliary path amplifiers. The cascading of the distortion-inverting circuit with the predistorter compensates for the non-linear behavior of the auxiliary path RF power amplifier (A2) thereby producing a composite signal at the output quadrature hybrid (200), in which RF carrier components from each amplifier combine constructively while distortion components cancel.

Radio frequency amplifier with reduced intermodulation distortion

Abstract: Apparatus and methods of broadband amplification with high linearity and low power consumption are described. An apparatus configured to amplify a signal includes an input transistor and an output transistor coupled together in a cascode configuration with the input transistor defining an input of the amplifier and the output transistor defining an output of the amplifier. A feedback network is coupled between the input and the output and is characterized by an impedance of substantially zero resistance and non-zero reactance. A method of amplifying a signal is also described. An input signal is received at an input; the input signal is amplified to provide an output signal at an output; and the output signal is sampled at the input through a feedback network characterized by an impedance of substantially zero resistance and ion-zero reactance. A method of making an apparatus configured to amplify a signal is also described.

Class D modulator with peak current limit and load impedance sensing circuits

Abstract: The OCL 200 receives two logic signals: the first, OC upper FET, is high when an over current condition exists in the upper FET 22 ; the second, OC lower FET, is high when an over current condition exists in the lower FET 24 . When the over current condition is in FET 22 , PMOS 212 turns on and injects current into the summing junction of the integrator 10 through Rcl. The net effect is turn off the upper FET 22 and turn on the lower FET 24 . This reduces the current in FET 22 . As far as amplifier 100 is concerned, the net effect is gain compression. Since upper FET 22 is on less and the lower FET 24 is on more, the gain of the audio signal is reduced. When the over current condition is in FET 24 , NMOS 213 turns on and pulls current out of the summing junction, turns the lower FET 24 off, and turns the upper FET 22 on. The net effect is to reduce the current in the lower FET. At audio frequencies, the gain is reduced.

Constant impedance for switchable amplifier with power control

Abstract: The present invention, generally speaking, provides an improved power amplifier that minimizes impedance changes as the power amplifier changes from one operational state to another. In an exemplary embodiment, the present power amplifier is based on the well-known cascode amplifier. In a cascode amplifier, a first transistor operates in the common-source (common emitter) configuration to convert the input signal voltage (or current) into an amplified current, and a second transistor operates in the common-gate (common-base) configuration to convert the output current from the first transistor into an output voltage.

Differential amplifier, operational amplifier employing the same, and liquid crystal driving circuit incorporating the operational amplifier

Abstract: An incidental offset voltage caused by discrepancies in material and workmanship can be averaged by (1) using two input transistors of a differential amplifier alternately, and (2) switching output signals from both the input transistors through two switches provided to an output end. Consequently, a downsized, less-power-consuming, highly-reliable differential amplifier which is insensitive to an incidental offset voltage caused by discrepancies in material and workmanship can be provided. Also, by employing such a differential amplifier, a less-power-consuming and highly reliable operational amplifier and a liquid crystal driving circuit capable of showing display of an upgraded quality can be realized.

Predistortion compensation for a power amplifier

Abstract: The invention relates to an amplifier arrangement for amplifying an input using a distorting main power amplifier such as one operating as a class AB amplifier. The method and apparatus add to the input signal to the main amplifier a predistortion signal intended to compensate for the distortion added by the main power amplifier. In accordance with the invention, the input to the predistortion circuit is modified by measuring peak-to-peak signal values of the distortion in the output of the main power amplifier. The peak-to-peak values are measured in a signal derived by comparing an output derived from the main amplifier with an output derived from the input signal. A digitally controlled processor iteratively modifies various phase and gain controls to adjust the output of the amplifier.

Self-biased, phantom-powered and feedback-stabilized amplifier for electret microphone

Abstract: A self-biased electret microphone amplifier with phantom powering which avoids the need for JFETs and depletion mode devices, both of which are not standard devices when using BiCMOS fabrication processes. Feedback is included to provide enhanced gain, dynamic range, linearity and temperature stability, without requiring filtering, large resistances or external components. A self-biased, phantom powered, differential MOSFET amplifier receives and pre-amplifies the microphone signal. Further amplification and feedback is provided by a differential amplifier and bipolar output amplifier which operates as a common emitter amplifier for the amplified microphone output signal and as an emitter follower amplifier for the feedback signal.

Linear power amplifier arrangement and method for its operation

Abstract: A linear power amplifier arrangement is used for providing a selectable amount of amplification to a radio frequency signal to be amplified. The arrangement comprises a first parallel amplifier branch and a second parallel amplifier branch and means for conducting the radio frequency signal to be amplified selectably to one of the parallel amplifier branches. Additionally it comprises in the first parallel amplifier branch a series connection of a predistorter and a nonlinear amplifier, where said predistorter is arranged to compensate for the nonlinearity of said nonlinear amplifier.

High-frequency power amplifier circuit and high-frequency power amplifier module

Abstract: An input matching circuit is provided having the output impedance-frequency characteristics wherein the output impedance shows a value approximately equal to that of the gate input impedance of the FET at the frequency of the objective signal to be amplified, and the output impedance shows a value not more than twice the gate input impedance of the FET at least at the entire frequencies from the frequency of the objective signal to be amplified through twice the frequency of the objective signal to be amplified so that the matching between the input previous stage circuit and the gate of the FET can be secured. Thereby, a high-frequency power amplifier circuit and a high-frequency power amplifier module, which can suppress the occurrence of distortion, perform stably, and get miniaturized, are configured.

A 1.5-V high drive capability CMOS op-amp

Abstract: A novel CMOS operational amplifier with a 1.5 V power supply is presented. It is based on a folded-mirror transconductance amplifier and a high-efficiency output stage. The amplifier achieves an open-loop gain and a gain-bandwidth product higher than 65 dB and 1 MHz, respectively. In addition, a 1 V peak-to-peak output voltage into a 500 /spl Omega/ and 50 pF output load is provided with a total harmonic distortion of -77 dB. This performance was achieved using maximum aspect ratios of 120/1.2 and 360/1.2 for the NMOS and PMOS transistors, respectively, and a quiescent current as low as 60 /spl mu/A for the driver transistors. The amplifier was implemented in a standard 1.2 /spl mu/m CMOS process with threshold voltages around 0.8 V. It dissipates less than 300 /spl mu/W.

Logarithmic amplifier with self-compensating gain for frequency range extension

Abstract: A progressive-compression logarithmic amplifier, amplifier stage, and method for increasing the bandwidth of a differential-input progressive-compression logarithmic amplifier are disclosed. The amplifier stage provides positive gain increases for decreases in the impedance of the load driven by the stage. When multiple amplifier stages of this type are cascaded, the gain increase in each stage compensates for high-frequency roll-off due to the input capacitance of the following stage. The compensating is activated by the roll-off effect itself, making the device self-compensating. This is preferably accomplished by providing a drive current sensing path that makes each node of the stage's differential output respond in opposition to the drive current drawn at the stage's other differential output--that is, an increase in drive current at one output node drops the voltage at the other output node.

A wide dynamic range transimpedance amplifier

Abstract: An integrated circuit transimpedance amplifier for an optical receiver is formed by a bipolar process comprising fixed value resistive elements in a network to provide AGC. The resistive elements are arranged in a parallel configuration and a transistor switching network is provided to enable at least one of said elements to be isolated from a gain stage of the amplifier thereby providing a means of varying amplifier gain.

Power sensing apparatus for power amplifiers

Abstract: In a power amplifier comprising a plurality of cascaded field effect transistors (FETs), a power sensing circuit for sensing the output power of the power amplifier comprising a FET device operative in a first linear mode and second saturated mode of operation, the FET having source, gate and drain electrodes; and a low value resistor connected between the source electrode and a reference potential for generating a voltage drop between the source and the reference potential such that when the FET operates in the saturation mode, the voltage drop is indicative of the output power of the power amplifier.

Wide-dynamic-range variable-gain amplifier

Abstract: A very-wide-dynamic-range amplifier with very low-noise in the high-gain mode and very high-input-overload in the low-gain mode. The amplifier utilizes two parallel signal paths, one a high-gain, low-noise path and the other a low-gain, high-input-overload path. Each path includes a gain-control capability so that the gain of each path, and the contribution of the gain of each path to the overall gain of the amplifier may be smoothly varied from a very low-gain to a very high-gain. Specific embodiments including input impedance matching capabilities are disclosed.

500 W, class E 27.12 MHz amplifier using a single plastic MOSFET

Abstract: In this paper, we report on the design and evolution of a 500 W, 27 MHz Class E amplifier. It doubles the operating frequency of previous high efficiency amplifiers using MOSFET transistors in the TO-247 package. Device criteria, circuit design, and amplifier performance characteristics are presented and compared to a HEPA computer model.

Integrated antenna switch having amplifier

Abstract: An antenna switch includes at least one signal path, including an amplifier device and a switch. The amplifier device includes an amplifier connected to a first inductor and to a first capacitor, which is grounded. The amplifier is voltage supplied via a second inductor. The switch includes a receiving isolation device, which is connected to a bypass capacitor connected to an antenna via a low pass filter. A first microstrip is connected to the bypass capacitor and to a DC switch. The first inductor and the first capacitor together with a shorted output transistor of the amplifier form a high impedance in receiving mode, thereby not affecting the receiving signal. The receiving isolation device is a signal wire.

Semiconductor amplifier circuit and system

Abstract: A semiconductor amplifier circuit is provided which comprises a cascode amplifier whose negative characteristic of output conductance is improved in at least a specific frequency range. The semiconductor amplifier (1) comprises a cascode amplifier (500) including cascaded transistors (101, 102) and means for improving the negative characteristic of output conductance (Gout) of the cascode amplifier (500) in at least a specific frequency range.

Power amplifier MMIC and mobile communication terminal

Abstract: A power amplifier MMIC has a first stage amplifier circuit having a transistor and matching circuits provided on input and output sides of the transistor; a plurality of final stage transistors connected in parallel; a first line connected between adjacent gates of the plurality of final stage amplifiers; a second line, connected between adjacent drains of the plurality of final stage amplifiers, for correcting an input signal phase shift caused by the presence of the first line; and an output matching circuit connected to one of connection points between the second line and the drains, and wherein an output of the first stage amplifier circuit is coupled to one gate of a final stage transistor whose drain is not connected to the output matching circuit, and the first stage amplifier circuit and the plurality of final stage transistors are arranged longitudinally alongside each other.