Showing papers on "Field-effect transistor published in 1973"

Liquid crystal display system with integrated signal storage circuitry

Abstract: Liquid crystal display systems having display panels in which a matrix array of reflective electrodes, as well as the individual addressing circuitry (field effect transistor) and electrical storage circuitry (capacitor) for each cell of the display panel, are formed on semiconductor backplates such that each reflective electrode forms one element or plate of the capacitor for the corresponding cell. Each field effect transistor is utilized to address an associated element of the matrix array, and the associated storage capacitor maintains the applied potential across the liquid crystal cell for a period sufficient for scattering centers to be formed in the liquid crystal material.

A two-dimensional mathematical model of the insulated-gate field-effect transistor

Abstract: This paper is concerned with the mathematical details of a numerical model of the insulated-gate field-effect transistor; a computer-aided analysis of the device, based on this model, appears separately A finite-difference scheme is presented for obtaining an approximate solution of a system of nonlinear elliptic partial differential equations describing the carrier distribution in such a device model In particular, our scheme allows the device current, as a function of the applied bias voltages, to be reliably calculated The results of numerical experiments appraising the accuracy of the method are also included

Current saturation and small-signal characteristics of GaAs field-effect transistors

Abstract: The model previously proposed by Turner and Wilson is developed in detail and compared with experiment. Deviations from Shockley's classical theory can be accounted for in terms of a single quantity Γ, which is related to E m the peak field for GaAs. A discussion of the physical mechanism of current saturtation shows that the formation of domains within the channel is hampered in a conventional GaAs FET. A y -parameter analysis is presented that permits calculation of transconductance and the unity current gain frequency f T . Measurements of drain current, transconductance, and f T versus gate voltage all show good agreement with values predicted by the theory. Estimates are given which show that the current saturation mechanism described will be important in the design of GaAs microwave FET's.

Subthreshold design considerations for insulated gate field-effect transistors

Abstract: A knowledge of subthreshold behavior in an insulated gate field-effect transistor is important for circuits with low leakage specifications. This paper discusses the effect of drain voltage on the subthreshold region as the channel length becomes shorter, the effect of substrate bias on both the shift in and the slope of the subthreshold curves, and the effect of temperature on the subthreshold current characteristics. It is shown that all these effects can be incorporated into a simple one-dimensional model.

Field effect transistor integrated circuit and memory

Abstract: An integrated circuit structure of a field effect transistor (FET) serially connected to a capacitor has the capacitor formed by one of the current flow electrodes of the FET and by a polycrystalline silicon (polysilicon) field shield. The structure includes, in a semiconductor (e.g., silicon) substrate, of, e.g., p-type conductivity, two spaced regions of opposite conductivity type to that of the substrate, e.g., n-type. One of the spaced regions serves as a first plate of the capacitor and as a first current flow electrode of the FET. The other region serves as a second current flow electrode of the FET. A first insulating layer on the substrate has a polysilicon layer on it covering the two spaced regions and is directly and ohmically electrically connected to the substrate. The portion of the polysilicon layer over the spaced region serving as the first plate of the capacitor serves as the second plate of the capacitor. A second insulating layer covers the polysilicon layer and a second layer of conducting material, e.g., aluminum, is provided on the second insulating layer. The second conductive layer overlies the space between the two spaced regions and serves as a gate electrode for the FET. When employed as a memory circuit, the spaced region of opposite conductivity type to the substrate which does not serve as the first plate of the capacitor is desirably a diffused bit/sense line and the second conducting layer serves as a word line.

Subthreshold characteristics of insulated-gate field-effect transistors

Abstract: A simple analytical model is developed for the subthreshold region of insulated-gate field-effect transistors (IGFET). For short channels, it is necessary to extend the model to include two-dimensional band-bending effects at the source in order to describe correctly the reduction in threshold caused by high drain and substrate voltages. The model is experimentally verified over a wide range of bias conditions and channel lengths and is compared with one- and two-dimensional numerical models.

Ferroelectric memory device

Abstract: A ferroelectric memory device utilizing the remanent polarization of a thin, ferroelectric film to control the surface conductivity of a bulk semiconductor and perform the memory function. The structure of the device is similar to a conventional MIS field effect transistor with the exception that the gate insulating layer is replaced by a thin film of active ferroelectric material comprising a reversably polarizable dielectric exhibiting hysteresis.

Steady state mathematical theory for the insulated gate field effect transistor

Abstract: A two-dimensional mathematical analysis is presented of the mechanisms of operation for an insulated gate field effect transistor (IGFET). Included in this analysis are qualitative and quantitative comparisons between conventional one-dimensional theory and a rigorous two-dimensional computer solution for the IGFET. It is shown that many characteristics of device operation deduced from conventional theory cannot be verified on a two-dimensional basis because of mechanisms not presently taken into consideration by the theory. A modified one-dimensional mathematical theory is therefore proposed, to account for these mechanisms, that is in adequate agreement with a rigorous two-dimensional computer solution for this semiconductor problem.

Process for fabricating MNOS non-volatile memories

Abstract: The switching speed of an MNOS field effect transistor is increased by a heat treatment in an ammonia rich atmosphere during processing. The transistor has an insulated gate structure comprising a layer of silicon nitride deposited on a layer of silicon oxide. After the formation of the silicon oxide layer and immediately prior to the formation of the silicon nitride layer on a surface thereof, the surface of the silicon oxide layer is heat treated in an ammonia enriched atmosphere to remove substantially all remaining oxygen atoms and molecules absorbed on the surface.

System for eliminating substrate bias effect in field effect transistor circuits

Abstract: An integrated circuit, formed on a common substrate, having one portion operated from a first source of operating potential and another portion operated from a second source of operating potential. Separate wells are diffused in said substrate for the connection thereto of the different voltages and a reference potential common to the two sources of operating potential is applied to the common substrate. Transistors having a given potential applied to their source electrodes are formed in the common substrate or in a well having the same given potential connected thereto for eliminating potential differences between the source and the substrate of the transistors.

Low power, high speed, high output voltage fet delay-inverter stage

Abstract: An integrated circuit and a method operating the circuit is disclosed wherein first and second MISFET transistors are connected with the source node of the first common with the drain node of the second and providing the output node of an inverter or delay stage. The output node is capacitively coupled back to the gate of the first transistor. A third transistor also connects the gate of the first transistor to a source of voltage, such as the drain voltage, in such a manner that the first transistor can be controlled and also such that a voltage higher than the drain voltage can be permitted on the gate of the first transistor. The first transistor is turned off and the second turned on to provide a logic ''''0'''' output, and conversely the first on and the seond off to provide a logic ''''1'''' output, with no power consumption in either state. To switch from a logic 0 output to a logic 1 output, the first transistor is switched on just prior to the time the second is being switched off so that as a result, the gate of the first transistor is ''''bootstrapped'''' to a voltage in excess of the drain voltage as a result of being capacitively coupled to the output node as the second transistor is switched off. The very high gate voltage results in very rapid switching of the first transistor to an output level equal to the drain voltage, yet results in excess power consumption only during the short switching cycle while both transistors are on. The same results can be achieved without using the second transistor if the gate node of the first transistor is switched on very rapidly. The circuit third transistor is switched on very rapidly. The circuit can be used as a delay stage for clock generators or as an inverter stage, depending upon the node selected as the data input.

Junction field effect transistor

Abstract: A junction field effect transistor having a "V" shaped upper gate, dividing said planar source and drain regions, formed by etching a (100) crystal oriented semiconductor material of one conductivity type and diffusing with material of opposite conductivity type.

Dielectric diode, fabrication thereof, and charge store memory therewith

Abstract: A dielectric diode is provided in accordance with the principles of this invention. The dielectric diode is in the form of a capacitor wherein one of the electrodes has a high contact barrier, e.g., 4 electron-volts, and the other has a low contact barrier, e.g., 1 electron-volt, giving the resulting structure a diode behavior. Illustratively, the electrode at the low contact barrier comprises a valve metal or a very reactive metal which has been anodized or oxidized to provide a layer region with a given concentration of positive ions. The resulting metal oxide is covered with a wide band gap insulator such as SiO 2 . The composite contact barrier from the conductor to the insulator is typically less than 1 eV and results from the transition layer region between the conductor electrode and the insulator layer. The wide gap insulator layer is covered on the opposite surface with another electrode which has a high contact barrier. Electronic current will tunnel easily from the first electrode into the insulator layer via the composite contact barrier and then will be collected by the second electrode as a relatively large tunnel current. However, the tunnel current from the second electrode, through the insulator and to the first electrode is relatively quite small at electric fields less than 10 6 volts/cm. A dielectric diode provided in accordance with the principles of this invention can be used to charge and discharge a capacitor, forming a memory cell. The charge on the memory capacitor can be sensed by a field effect transistor.

Composite transistor device with over current protection

Abstract: The base-emitter junctions of a power transistor and an auxiliary transistor are paralleled. The smaller collector current of the auxiliary transistor can be sampled so as to indirectly sample the larger collector current of the power transistor. When the indirect sampling indicates that the collector current in the power transistor is tending to exceed its rated maximum value, its base and emitter electrodes are clamped. This prevents increase in the base-emitter potential of the power transistor and consequently increase of its collectorto-emitter current.

IGFET with gate protection diode and antiparasitic isolation means

Abstract: Described are insulated gate-type field effect transistors used in capacitive memory circuits and having protective diodes for protecting the insulating films below the gate electrodes from electrical breakdown, in which parasitic transistor action which might be caused by minority carriers injected into semiconductor substrates by noise signals applied to the protective diodes are eliminated by means for suppressing injection of minority carriers or by means for preventing injected minority carriers from reaching the drain regions of the field effect transistors.

Logic circuit arrangement employing insulated gate field effect transistors

Abstract: A logic circuit arrangement consisting of insulated gate field effect transistors of opposite channel types wherein the drain electrode of a single first insulated gate field effect transistor of one channel type is connected to the drain electrode of at least one second insulated gate field effect transistor of the opposite channel type constituting a logic gate. The gate electrode of second transistor is supplied with a data signal and the gate electrode of first transistor and the source electrode of second transistor are supplied with clock pulse signals bearing a complementary relationship with each other. The source electrode of first transistor may receive a clock pulse signal supplied to the source electrode of second transistor or constant voltage; and an output signal from the logic circuit is delivered from the junction of the first and second transistors.

Application of facet-growth to self-aligned schottky barrier gate field effect transistors

Abstract: A semiconductor device and particularly a self-aligned Schottky barrier gate field-effect transistor is made by epitaxial growth of facets corresponding to the source and drain regions on a surface of a semiconductor body through spaced apart preferably elongated windows in a masking layer and overgrowing edge portions of the masking layer at the windows to form overgrown portions on the facets. The channel region of the transistor is previously formed in the semiconductor body, preferably by epitaxial growth of a layer on a surface of a semiconductor body having a semi-insulating layer adjoining the surface. After removal of the masking layer, the Schottky barrier gate is self-aligned by deposition of metal on the unshielded portions of the planar surface between the facets.

Multilayered vertical transistor having reach-through isolating contacts

Abstract: Logic circuits for performing the INVERTER and NOR functions, and monolithic integrated structures for realizing the circuits. The basic circuit comprises PNP transistor and an NPN transistor. The emitter of the PNP transistor has its base grounded and its collector connected to the base of the NPN transistor having its emitter grounded. The logic signal input is at the base of the NPN transistor. The output is taken at the collector of the NPN transistor and is the inverse of the input. Two such basic circuits are interconnected to provide the NOR function.

Method for manufacturing ion implanted insulated gate field effect semiconductor transistor devices

Abstract: A method for manufacturing insulated gate field effect transistor devices utilizing ion implantation for elimination and suppression of mobile ion contamination is described and comprises bombarding and implanting hydrogen or helium into the dielectric insulating layer of an insulated gate field effect transistor at relatively low ion energy, followed by a comparatively low temperature anneal.

Source-drain breakdown in an insulated gate, field-effect transistor

Abstract: In IGFET operation, electrical breakdown between source and drain has been attributed to drain-junction avalanche breakdown. IGFET source-drain breakdown occurs at voltages less than drain-junction avalanche breakdown; this voltage decreases with decreasing channel length. Source-drain breakdown can be induced by increasing gate biasing voltage. Moreover, a large breakdown current is often sustained after removing the gate voltage. In this situations the IGFET "latches" in a source-drain breakdown mode. IGFET source-drain breakdown can be attributed to the extrinsic (or parasitic) bipolar transistor in parallel with the intrinsic IGFET structure. Carrier multiplication within the drain space-charge layer produces a substrate potential distribution that turns on this parasitic region; thus, IGFET source-drain breakdown is equivalent to emitter-collector breakdown (BV CEX ) for a bipolar transistor. Our mathematical model semi-quantitatively shows: the IGFET source-drain breakdown characteristics; the "latching"phenomenon; and the reduction of source drain breakdown voltage with decreasing channel length.

Method for making FET circuits

Abstract: An integrated circuit and process for manufacturing same is disclosed. The integrated circuit comprises both depletion and enhancement mode field effect transistors, each having silicon gates and self-aligned gate regions. The process includes forming a thick oxide layer on the substrate, removing the thick oxide at the transistor sites, forming a thin oxide at the transistor sites, masking selected transistor sites to selectively implant ions at the other sites, depositing a polysilicon layer over the slice and patterning the polysilicon layer to form gate electrodes, removing the thin oxide using the polysilicon gate electrodes as masks, diffusing the source and drain regions, forming an insulating oxide, then applying the source drain and gate contacts and interconnects.

Computer analysis of the double-diffused MOS transistor for integrated circuits

Abstract: The effective length of an MOS transistor can be made narrow by using double diffusion similar to a bipolar transistor. Computations were conducted for an n-channel double-diffused transistor with different surface concentrations, channel lengths, channel gradients, surface-states densities, and substrate concentrations. A shorter channel length and a higher surface-state density, e.g. \langle1, 1, 1\rangle crystal, gave a higher drain current and transconductance. The maximum transconductance in many cases occurs at low gate voltages. The computations indicate that a gain-bandwidth product in the gigahertz range can be expected when the graded channel region is less than 1 µm. The difference between an n-type substrate and a p-type substrate is not substantial. The analysis is also useful in predicting the performance of any integrated logic circuit using the diffused enhancement transistor as the active switch and a depletion-mode transistor (without a diffused channel) as the load device. The computation indicates that satisfactory performance can be obtained using a load device with the same geometry and an ON voltage of only a fraction of a volt, This revelation indicates that double-diffused channel MOS transistors not only give higher speed but also smaller chip area for integrated circuits and a lower supply voltage (hence less power dissipation).

Electrically erasable floating gate fet memory cell

Abstract: A read-mostly memory cell is disclosed comprising a floating gate avalanche injection field effect transistor storage device equipped with an erasing electrode. The memory portion of the erasable storage devices comprises a P channel FET having a floating polycrystalline silicon gate separated from an N-doped substrate by a layer of silicon dioxide. The erasing portion of the device comprises an erasing electrode separated from the polycrystalline silicon floating gate by a thermally grown layer of silicon dioxide having a leakage characteristic which is low in the presence of low electrical fields and high in the presence of high electrical fields. The floating gate is heavily doped with boron which also partially dopes the thermally grown silicon dioxide layer. The floating gate is charged negatively by avalanche breakdown of the FET drain while the erase gate is grounded to the substrate. The floating gate is discharged (erased) upon the application of a positive pulse to the erase electrode with respect to the semiconductor substrate causing electrodes on the charged floating gate to leak through the thermal oxide to the erasing electrode.

Method of forming self-aligned field effect transistor and charge-coupled device

Abstract: A semiconductor device containing in a single semiconductor body a self-aligned Field Effect Transistor and a Charge-Coupled Array having an improved capacity for storing charges. The device is formed by depositing both polysilicon and silicon nitride layers over a silicon dioxide layer on the surface of a silicon body and selectively etching these layers so that suitable dopants may be diffused or ion-implanted into selected areas of the underlying silicon body to form, in the same semiconductor body, an improved charge-coupled array having an improved self-aligned Field Effect Transistor associated therewith. This process not only results in a device in which the chance of an inversion layer under the oxide on the surface of the device is substantially reduced, but also provides a self-aligned Field Effect Transistor having a thinner gate oxide and a charge-coupled array that has an increased capacity for storing charges. The improved array so formed also has, during operation, zero spaced depletion regions so that unwanted electrical discontinuities between or within the depletion regions of the charge-coupled array are avoided. Because zero spacing is achieved by using these thin conducting layers, the metal phase lines can be made narrow thus leaving openings in the charge transfer channel making the device particularly suitable for imaging applications.

Method of making isolated complementary monolithic insulated gate field effect transistors

Abstract: Complementary insulated gate field effect transistors are formed in a thin semiconductor layer of a first conductivity type by first forming a dielectric layer on a surface of the semiconductor layer. A polycrystalline support is then formed on the dielectric layer. A lightly doped tub region of a second conductivity type is formed in the semiconductor layer extending to the dielectric layer. The lightly doped tub region is preferably formed by carrying out a conventional diffusion operation, then removing a portion of the thickness of the semiconductor layer which contains the highest dopant concentration. Regions serving as source and drain electrodes of a first and second field effect transistor are then formed in the lightly doped tub region and in the semiconductor layer. Gate electrodes are provided over an insulating layer on the surface of the semiconductor layer to complete fabrication of the complementary devices. The gate electrodes may be formed after the source and drain electrodes, or before them, in a self aligned embodiment.

Current source biasing circuit

Abstract: A first field effect transistor is employed as a current source with another like field effect transistor biased close to the threshold voltage thereof connected through a semiconductor junction to the gate of the first field effect transistor so that the current output of the source is substantially independent of supply voltage variations and the turn-on voltage of the first field effect transistor is determined by the forward voltage of the junction.

Semiconductor memory device and field effect transistor suitable for use in the device

Abstract: Semiconductor memory device in which charge carriers are injected between a semiconductor surface and a gate electrode separated from the semiconductor surface by an insulating layer to effect a change in the characteristics of the device.

GaAs field-effect transistors with ion-implanted channels

Abstract: Schottky-barrier-gate n channel depletion-mode field-effect transistors have been fabricated in GaAs by the use of sulphurion implantation directly into semi-insulating Cr-doped substrates to produce the channel. This technique eliminates the need for the growth of a thin epitaxial layer, as is usually done, and results in better uniformity of device characteristics over the wafer area. Performance of these devices at 1 to 12 GHz is described, and low-frequency characteristics are given.

Method for forming silicon conductive layers utilizing differential etching rates

Abstract: A method for forming contoured electrodes of polycrystalline silicon by grading the concentration of dopant diffused into the silicon layers during the deposition process. Upon etching the silicon after deposition to form electrodes, e.g., the gate electrode of a field effect transistor, the electrode is desirably tapered. Conductive and insulator layers subsequently deposited atop the tapered electrode are less subject to cracking and lifting off than standard electrodes.