Showing papers on "Field-effect transistor published in 1977"

Very small MOSFET's for low-temperature operation

Abstract: The improvements in the device characteristics of n-channel MOSFET's that occur at low temperatures are considered in this paper. The device parameters for polysilicon gate FET's with channel lengths of the order of 1 µm have been studied both experimentally and theoretically at temperatures ranging from room temperature down to liquid nitrogen temperature. Excellent agreement was found between the experimental dc device characteristics and those predicted by a two-dimensional current transport model, indicating that device behavior is well understood and predictable over this entire temperature range. A device design is presented for an enhancement mode FET with a channel length of I µm that is suitable for operation at liquid nitrogen temperature.

Insulated gate field-effect transistor read-only memory cell

Abstract: A read-only memory cell formed from a single insulated gate field-effect transistor may be selectively programmed by being operated under suitable biasing conditions to cause some of the electrons flowing between the source and drain to acquire sufficient energy to be injected into and trapped in the insulating material separating the channel from the gate electrode. The trapped electrons cause a change in the current-voltage characteristics of the transistor which may be detected during reading of the memory cell most easily by reversing the polarity of the source and the drain. An array of such cells may be utilized as a ROM, PROM or EPROM.

Insulated gate field effect transistor

Abstract: An insulated gate field effect transistor is formed of a drain region of a first conductivity type which faces both of the major surfaces of a semiconductor substrate, a frame region of a second conductivity type which faces the one major surface of the semiconductor substrate, a base region of the second conductivity type which faces the one major surface and is connected to the frame region, a PN junction being formed between the base region and the drain region, and a source region of the first conductivity type which faces the one major surface and is formed in the base region as if being surrounded thereby. The insulated gate field effect transistor is also provided with a source electrode which short-circuits the frame region and the source region, a drain electrode which is provided on the drain region facing the other major surface of the substrate, and a gate electrode which is provided on the base region facing the one major surface through a gate insulating layer.

Insulated gate field-effect transistor read-only memory array

Abstract: An array of read-only memory cells is formed from a plurality of insulated gate field-effect transistors. Information may be programmed into individual transistors within the array by application of selected potentials to the connecting lines of the array. An individual cell is programmed by causing some of the electrons flowing between the source and drain to acquire sufficient energy to be injected into and trapped in the insulating material separating the channel from the gate electrode. The trapped electrons cause a change in the current-voltage characteristics of the transistor, which may be detected during reading of the memory cell most easily by reversing the polarity of the source and the drain. Embodiments of such an array are shown and may be utilized as a ROM, PROM and EPROM.

Chemical-sensitive field-effect transistor

Abstract: The invention relates to an insulated-gate field effect transistor which is adapted for detecting and measuring various chemical properties such as ion activity in a solution. The device has a chemically sensitive layer which overlies a portion of a substrate other than that covered by the gate insulator. When this chemically sensitive layer is exposed to a solution or other substance, the electric field in the substrate is modified which changes the conductance of the channel between a source region and a drain region. The change in conductance is related to the chemical exposure and can be detected with a current meter.

Current control circuit for light emitting diode

Abstract: The current in a semiconductive light emitting diode (LED), driven by an insulated gate field effect transistor (IGFET) switch, is stabilized by a current control circuit including a comparator type feedback network, which stabilizes the voltage at a node located between said switch and the series connection of a ballast resistor and the LED.

Electrically erasable non-volatile semiconductor memory

Abstract: A non-volatile semiconductor storage device comprising a dual gate field effect transistor in which an electrically floating gate acts as a charge storage medium. An insulating layer of an appropriate dielectric material separates the floating gate from the active portion of the transistor. A predetermined section of this insulating layer is relatively thin to permit this section of the floating gate to be relatively close to a corresponding predetermined section of the transistor, thus facilitating the transfer of charges between the transistor substrate and the gate. When charges reach the floating gate either through tunneling or avalanche injection, they are entrapped and stored there, thus providing memory in the structure. That is, the electric field induced by these charges is maintained in the transistor even after the field inducing force is removed. Erasing is achieved by removing the charges from the floating gate by reverse tunneling through the relatively thinner insulator region.

Insulated gate field effect transistor with source field shield extending over multiple region channel

Abstract: In an insulated gate field effect transistor having a source region and a drain region of the P-conductivity type which are disposed in surface portions of a semiconductor substrate of the N-conductivity type in a manner to be spaced apart from each other, a gate electrode being disposed through an insulating film on the substrate between the source region and the drain region, an insulated gate field effect transistor wherein said drain region is disposed apart from said gate electrode, two regions of an intermediate region and a high resistance region which are of the P-conductivity type and which successively extend from said drain region towards the side of said gate electrode are disposed in surface portions of the substrate situated between said drain region and said gate electrode, said intermediate region having an impurity concentration lower than that of said drain region, said high resistance region having an impurity concentration lower than that of said intermediate region, and a source electrode extends over and beyond said gate electrode and said high resistance region through said insulating film and terminates over said intermediate region.

Optimum design of triode-like JFET's by two-dimensional computer simulation

Abstract: Design criteria of triode-like JFET's are studied by fully utilizing two-dimensional numerical analysis. The current is caused by tlie carriers injected over a potential barrier in a depleted channel. In contrast to normal pentode-like FET'S, the drain field plays an important role reducing the barrier height and thus causing triode-like I-V characteristics. Triode-like characteristics depend strongly on device geometry. This operation can be realized only in short gate devices. The channel thickness a is an essential parameter in determining the operational mode. The devices operate as triodes or pentodes corresponding to thin or thick channels, respectively. If applied to low-resistance load direct-drive circuits, the mixed characteristics situated between the triode- and pentode-like ones, are more desirable when compared to pure triode-like ones, This is because of their low on-resistance and high ac power efficiency. The gate-drain distance l gd is also essential in determining breakdown voltage. The design criteria are discussed and an optimum design specified on the N D (channel doping)- a and N_{D} - l_{gd} planes with respect to triode-like characteristics, circuit application and breakdown phenomena. Calculated results are compared with experiments and good agreement is found without using any adjustable parameters. The present design criteria will be useful for designing triode-like JFET's.

Voltage-controlled type oscillator

Abstract: A voltage-controlled type oscillator includes a differential amplifier constituted by a first and second transistors for establishing a current, as the collector current of the second transistor, proportional to an input control voltage, and an oscillating device for producing an oscillatory signal whose frequency is determined by that current. An element having a p-n junction is connected between the second transistor and the oscillating device and a further transistor is connected between the first transistor and a power source. A portion of the current flowing from the oscillating device is divided as a base current to the abovementioned further transistor whereby an adverse influence by the base current of the second transistor is eliminated. Thus the oscillation frequency is accurately proportional to the input control voltage.

System for determining the current-voltage characteristics of a photovoltaic array

Abstract: A nonlinear load circuit, consisting of a transistor and a resistor in series, is provided for the photovoltaic array under test. Base bias for the transistor is supplied via the source-to-drain path of a field effect transistor (FET). A ramp signal is fed to the gate of the FET. As a result of the nonlinear relationship between the gate voltage and source-to-drain current of the FET, equal ramp steps result in a nonlinear effective load for the array under test. This produces a very gradual change in load impedance for each ramp step in the regions of high current output from the array ("current mode"), and relatively greater changes in load impedance for each ramp step at output levels of lower current and higher voltage from the array ("voltage mode"). Advantageously, the array is illuminated by a pulsed flash lamp. A photosensor detects the light level incident on the array, and comparison circuitry provides a "sample" pulse each time that the incident light level is at a selected value. This "sample" pulse gates a pair of sample and hold circuits that respectively sample the array output current and voltage under the load condition determined by the present ramp step. Consecutive like operations facilitate measurement and plotting of the complete current-voltage curve.

Two and three mask process for IGFET fabrication

Abstract: Semiconductor wafer processes employing two and three masks are disclosed for fabricating a plurality of insulated gate field effect transistors (IGFETs) to be used singly as discrete devices or interconnected as integrated circuits on the wafer by means of diffused regions at a first level and a composite of polysilicon and metal silicide layers at a second level. The first mask of the two-mask process is used in opening windows through a thick oxide layer covering the wafer for the gate and diffused regions including the source and drain regions. After forming a thin oxide layer in these windows, the wafer is coated with successive layers of polysilicon and silicon nitride. Then, a second masking operation yields a pattern out of the polysilicon-nitride layer including gate electrodes and a top-lying interconnection level which abuts to openings etched through the thin oxide layer. Doping impurities are diffused therethrough to form source and drain regions and crossunders. After etching the nitride layer a silicide forming metal is deposited and sintered to form a silicide layer on all exposed silicon surfaces lowering the sheet resistance of the polysilicon layer and joining the interconnection pattern with the source and drain regions. The process is completed by removing the remaining unreacted metal using a maskless aqua regia etch.

Method of making a V-MOS field effect transistor for a dynamic memory cell having improved capacitance

Abstract: This disclosure relates to a method of making a V-MOS field effect transistor which does not require the extra steps of epitaxial growth in order to form the source area of the transistor. The formation of the source area is achieved by masking the silicon substrate, opening an aperture in the mask and then etching the silicon substrate in such a manner as to undercut the mask so that the mask provides a shield to subsequent ion implanting of the source area. Both P and N type dopants can be separately implanted with different energy levels so as to form an enhanced PN junction capacitance for the device. Such a field effect transistor can be achieved without the formation of a graded dopant concentration in the channel between the source and drain areas of the transistor and is provided with enhanced source capacitance.

Ion-implanted threshold tailoring for insulated gate field-effect transistors

Abstract: This paper develops a general threshold equation for long-channel insulated gate field-effect transistors which accounts for the effects of ion-implant profiles used in threshold tailoring. Although any integrable function used to describe the nonuniform doping will yield an analytical expression for threshold, a Gaussian function is chosen because it accurately describes the implanted profile following proper annealing, regardless of subsequent high-temperature steps during fabrication. Most profiles of interest are quasi-neutral, i.e., the spatial dependence of the majority carriers in the undepleted bulk is adequately described by the doping profile, but the threshold equation is shown to be an excellent approximation for non quasi-neutral profiles as well. Comparison with experimental results show the analytical expression to be in good agreement with data over a wide range of implant conditions and starting substrate resistivity.

Electronic switching circuit using junction type field-effect transistor

Abstract: In an electronic switching circuit using a junction type field-effect transistor, a capacitor is connected between the gate electrode of the transistor and a control pulse source. The capacitor is cooperative with a rectifying action of the gate electrode of the transistor to supply to the gate of the transistor a switching voltage which is different from the potential level of the control pulse from the control pulse source and is DC-restored following an input signal applied to the transistor.

Power field effect transistors

Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) having high switching speed capabilities is shown. The high switching speed is facilitated by narrow channel length which is defined by the difference in lateral diffusion junctions of the P substrate and N source diffusions. The high current capability is produced by the large channel width. The high voltage capability is caused by the use of FET substrate P diffusions designed to be located apart from one another by very small distances. Unbiased or floating P diffusions are designed to flank the outer peripheries of P substrate diffusions. The close proximity of the adjacent P substrate diffusions reduces the electric field in the curvature portion of the P diffusion junctions in the N - silicon body at their inner peripheries, while the presence of the unbiased P diffusions at the appropriate distance from the outer peripheries of P substrate diffusions reduces the electric field in the curvature region of the P substrate diffusions at their outer peripheries. The N silicon body forms the drain region.

Computer simulation of gallium arsenide field-effect transistors using Monte-Carlo methods

Abstract: A gallium arsenide planar field-effect transistor (f.e.t.) structure is simulated using a particle-mesh computer model. The model incorporates two dimensions in configuration space and three dimensions in k-space; with a full description of the material scattering cross-section which is implemented using Monte-Carlo techniques. The f.e.t. static characteristic has been calculated together with the lumped equivalent-circuit paramters. A comparison is made between devices with and without substrate. Detailed information about electrostatic potential and valley population profiles is presented for the first time. Cole-Cole plots of complex output impedance are used in determining device frequency response.

Voltage detection circuit composed of at least two MOS transistors

Abstract: A voltage level detection circuit comprises a first MOS transistor having the gate and the drain connected together with a power source voltage V DD via a resistor and the source grounded and a second MOS transistor having the gate connected with the drain of the first MOS transistor and the source grounded via a resistor. The circuit functions to compare the power source voltage V DD with a sum of the threshold voltage levels of the first and second MOS transistors, whereby voltage detection outputs are developed at the source of the second MOS transistor.

A new approach to the theory and modeling of insulated-gate field-effect transistors

Abstract: Consideration of basic charge relationships in the IGFET has led to a new formulation of the theory of the device which allows model characterization in a more general manner, and with greater accuracy, than previously achieved. The contribution of the mobile channel charge to the silicon surface potential, which is believed to have a significant influence on the device characteristics, is taken into account in this approach. Accurate device modeling is achieved over a very wide range of operation, extending from weak channel (subthreshold) to high level channel conditions. An important feature of the model is that it is expressed in terms of a constant effective channel mobility. Further, the current and charge relationships involved take the form of a single set of analytic closed-form expressions in terms of the terminal voltages for all conditions of device operation, and are thus appropriate for CAD implementation. The scope and accuracy of this approach to IGFET modeling are demonstrated by comparisons between measured and theoretical dc and small-signal characteristics for sample metal and silicon gate devices.

Method of making an insulated gate field effect transistor by implanted double counterdoping

Abstract: An insulated gate field effect transistor having spaced highly doped source and drain regions with less highly doped source and drain extensions, which define the ends of the channel of the transistor, has both the source and drain extensions and the channel of the transistor defined in a controllable manner by the steps of forming a continuous zone of the same conductivity type as the source and drain regions in the space between these two regions and then counterdoping a portion of this layer.

Process for making field effect and bipolar transistors on the same semiconductor chip

Abstract: A process and the resulting structure for making metal oxide silicon field effect transistors and vertical bipolar transistors on the same semiconductor chip with the devices being dielectrically isolated from each other. The process does not require an epitaxial layer. The bipolar devices have utility as cross-chip or off-chip drivers or can be utilized for analog circuitry.

Membrane deformographic display, and method of making

Abstract: A MEMBRANE DEFORMOGRAPHIC DISPLAY, AND METHOD OF MAKING ABSTRACT OF THE DISCLOSURE A deformographic membrane display system in which a semiconductor substrate, for example silicon, has an insulating layer such as SiO2 formed thereon with an array of holes formed in the insulating layer. Alternatively, the insulating layer may be omitted, with the holes being formed in the substrate. A reflec-tive membrane, including a thin metal layer, is formed over the surface in which the holes are formed. Electrodes are formed in the silicon substrate directly beneath or in each of the holes. Control circuitry, which for example, may be formed utilizing metal oxide semiconductor field effect transistor (MOSFET) technology and/or bipolar technology, is formed in the silicon substrate for selectively energizing the electrodes. The portion of the membrane over a given hole is deformed in response to the electrode thereunder being energized by the control circuitry.

On the origin of leakage currents in silicon-on-sapphire MOS transistors

Abstract: n-channel n-p-n metal-oxide-semiconductor transistors (MOST's), fabricated in thin films of silicon-on-sapphire, exhibit values of source-to-drain leakage currents (I L )which vary from wafer to wafer, typicaily from 10-11to 10-7A/mil of channel width. Conversely, p-channel (p-n-p) devices exhibit low leakage current values in the range of 10-11∼ 10-10A/mil of channel width, consistent from wafer to Wafer. A model of a high concentration of donorlike states in the silicon in the vicinity of the Al 2 O 3 -Si interface creating a back-surface Conductive channel is proposed to account for both the inconsistently high n-channel and consistently low p-channel leakage current values. Experimental measurements of I L , which support the general conclusions of the model, are presented. I L is shown to be a strong function of a) the annealing temperature of the sapphire substrate prior to film growth, b) the silicon-film growth rate, c) the impurity concentration profile in the channel region, and d) the device geometry. These measurements show that the dominant factor controlling the overall magnitude of I L is the state of the Al 2 O 3 -Si interface immediately prior to silicon-film growth. A set of silicon-film growth conditions and device processing steps is outlined which achieve consistent n- and p-channel leakage current values of less than 10-9A/mil of gate width.

Characterization of silicon-on-sapphire IGFET transistors

Abstract: Under dynamic operation conditions, the potential of the floating substrate in a silicon-on-sapphire (SOS) device is primarily controlled by the capacitive coupling of the substrate to other device terminals. However, a key parameter that plays a major role in defining that potential during switching is the avalanche multiplication current produced by the channel current carriers in the surface space charge region adjacent to the drain. A closed form expression is derived for the avalanche current, enabling the development of a nonlinear equivalent circuit model of the device. Comparison of measurements with device terminal characteristics, as well as the switching behavior of the device, shows good agreement.

Simulation of semiconductor devices

Abstract: The simulation of semiconductor devices is a powerful means for optimizing the performance of semiconduc tor circuits and devices. various classes of semi conductor models exist, but accurate simulations re quire exact ("total") computer models. The exact models allow the use of arbitrary initial conditions and internal distributions and describe the device accurately over wide ranges of operation.This article discusses the leading numerical formula tions used to generate exact semiconductor models and describes the simulation of an NP junction, a bipolar transistor, and a MOS field effect transistor using exact models.

Low‐noise and high‐power GaAs microwave field‐effect transistors prepared by molecular beam epitaxy

Abstract: The low‐noise FET’s prepared on molecular‐beam‐epitaxial (MBE) layers have a noise figure of 1.9 dB with a corresponding gain of 11 dB at 6 GHz. The power FET’s can produce 1.3 W at 4.4 GHz (1‐dB compression) with a gain of 10 dB and a power‐added efficiency of 35%. The influence of substrate preparation on Hall mobility for very thin layers was also studied and there is no evidence of Cr diffusion from the substrate at the MBE growth temperature.

Process for fabricating insulated-gate field-effect transistors with self-aligned contacts

Abstract: The specification describes a process for making an insulated-gate field-effect transistor wherein a silicon nitride mask is deposited above the surface of a semiconductor body and is used in one embodiment of the invention in conjunction with a refractory gate member (1) as a mask in the formation of the source and drain regions by the ion implantation of conductivity-type-determining impurities on both sides of the gate and (2) as a mask in the formation of contact holes to the source and drain regions of the transistor for the subsequent provision of metal contacts to these regions. In another embodiment, there is described a process for forming source and drain contacts wherein the mask for the formation of contact holes by oxide etching is also the pattern definition and lift-off mask for the formation of metal contacts to the transistor.

Junction gate type gaas field-effect transistor and method of forming

Abstract: The invention discloses a heterojunction Type GaAs field-effect transistor of the type in which a channel region consists of an n-type GaAs layer with a higher mobility and a gate region consists of a p-type Ga 1-y Al y As layer which is grown heteroepitaxially. The length of the gate is of the order of microns, and a gate, source and drain electrodes are self-aligned. The gate region is etched in the form of a mushroom with the use of an etchant which etched the GaAlAs layer and the Ga-As layer at different etching rates so that the gate, source and drain electrodes may be formed by only one vacuum deposition of a metal such as aluminum.

Dependence of GaAs power MESFET microwave performance on device and material parameters

Abstract: The results of recent X-band measurements on GaAs Power FET's are described. These devices are fabricated with a simple planar process and at least 1-W output power at 9 GHz with 4-dB gain has been obtained from more than 25 slices having carrier concentrations in the range 5 to 15 × 1016cm-3. The highest output powers observed to date are 1.0 W at 11 GHz and 3.6 W at 8 GHz with 4-dB gain. Devices have had up to 46-percent power-added efficiency at 8 GHz. The fabrication process is briefly described and the factors contributing to the high output powers reported here are discussed. Some of these factors are epitaxial carrier concentration near 8 × 1016cm-3, good device heatsinking, and low parasitic resistance. The observed dependence of microwave performance on total gate width, gate length, pinchoff voltage, epitaxial doping level, etc., is described.