Showing papers on "Integral nonlinearity published in 1996"

A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 /spl mu/m CMOS

Abstract: A 13-b 5-MHz pipelined analog-to-digital converter (ADC) was designed with the goal of minimizing power dissipation. Power was reduced by using a high swing residue amplifier and by optimizing the per stage resolution. The prototype device fabricated in a 1.2 /spl mu/m CMOS process displayed 80.1 dB peak signal-to-noise plus distortion ratio (SNDR) and 82.9 dB dynamic range. Integral nonlinearity (INL) is 0.8 least significant bits (LSB), and differential nonlinearity (DNL) is 0.3 LSB for a 100 kHz input. The circuit dissipates 166 mW on a 5 V supply.

A stereo multi-bit /spl Sigma//spl Delta/ D/A with asynchronous master-clock interface

Abstract: An oversampling DAC that generates low-jitter, synchronous and oversampled clock internally uses an on-chip digital phase-locked loop (DPLL) and a digital sample-rate converter to decouple the DAC conversion rate from the audio sample rate. This allows the DAC to be driven by an independent low-jitter clock source that minimizes jitter-induced amplitude errors. The DAC uses a second-order /spl Sigma//spl Delta/ modulator in combination with a 17-level quantizer to achieve greater than 110 dB theoretical SNR and reduced out-of-band noise relative to higher-order 1b modulators. The problem of severe element matching in multi-bit DACs is addressed by applying a data-directed scrambling technique on the thermometer-decoded modulator output that modulates DAC element mismatch errors out of band.

Nonlinearity correction of the integrated time-to-digital converter with direct coding

Abstract: A method is presented for automated identification and correction of the nonlinearity error of the time-to-digital converter (TDC) with delay-line coding and 200 ps resolution, integrated on a single Field Programmable Gate Array (FPGA) device. The nonlinearity error is estimated using a statistical method based on a sufficiently large number N of measurements of random input time intervals having a uniform distribution within the input range of TDC. Then, the resulting estimate of the error function is used for training a two-layer neural network (NN) designed for correction of the nonlinearity error. Training of the NN is based on the fast Levenberg-Marquardt (LM) learning rule and the goal is to minimize the maximum nonlinearity error of the TDC. Experimental tests have shown, that using a relatively small number of N=5/spl times/10/sup 4/ identification measurements the maximum nonlinearity error of a TDC may be reduced from 1.37 LSB (least significant bit) to about 0.12 LSB (24 ps).

A 200 mW, 1 Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller

Abstract: This paper describes the design and implementation of a fully monolithic 16-b, 1 Msample/s, low-power A/D converter (ADC). An on-chip 32-b custom microcontroller calibrates and corrects the pipeline linearity to within 0.75 LSB integral nonlinearity (INL) and 0.6 LSB differential nonlinearity (DNL). High speed and low power are achieved using a pipelined architecture. Errors resulting from capacitor mismatches, finite op-amp open loop gain, charge injection and comparator offset are removed through self-calibration. Coefficients determined during calibration are stored on chip, digitally correcting the pipeline ADC in real time during normal conversion, Full-scale errors are removed through self-calibration and an-chip multiplication. Linearity errors due to capacitor voltage coefficients are reduced using a curve fit algorithm and on-chip ROM. Digital cross-talk errors resulting from the microcontroller running at a rate of ten times the analog sampling rate have prevented implementations of fully monolithic converters of this performance class in the past. Mismatches in cross-talk due to different digital timing between calibration and correction lead to linearity errors at critical correction points. Experimental analysis and circuit techniques which overcome these problems are presented.

BIST for D/A and A/D converters

Abstract: The expense of specialized equipment can be a problem in testing high resolution D/A converters. A BIST alternative that tests offset voltage, integral nonlinearity, differential nonlinearity, and gain error without such equipment or the use of a digital signal processor or microcontroller shows promise. We also extend the same technique to test a wide range of A/D converters.

A new digital test approach for analog-to-digital converter testing

Abstract: A fully digital built-in self-test (BIST) for analog-to-digital converters is presented in this paper. This test circuit is capable of measuring the DNL, INL, offset error and gain error, and mainly consists of several registers and some digital subtracters. The main advantage of this BIST is the ability to test DNL and INL for all codes in the digital domain, which in turn eliminate the necessity of calibration. On the other hand, some parts of the analog-to-digital converter with minor modifications are used in the BIST simultaneously. This also reduces the area overhead and the cost of the test. The proposed BIST structure presents a compromise between test accuracy, area overhead and test cost. The BIST circuitry has been designed using CMOS 1.5 /spl mu/m technology. The simulation results of the test show that it can be applied to medium resolution analog-to-digital converter or high resolution pipelined analog-to-digital converter. The presented BIST shows satisfactory results for 9-bit pipelined analog-to-digital converter.

A 14-b 2.5 MSPS pipelined ADC with on-chip EPROM

Abstract: A 14-b 2.5 MSPS, multistage pipeline, subranging analog-to-digital converter is presented. In addition to conventional laser-wafer-trim, on chip, "write once" EPROM is used to calibrate inter-stage gain errors at package sort. Integral nonlinearity errors as small as /spl plusmn/1.5 LSB and differential nonlinearity errors of /spl plusmn/0.5 LSB have been achieved. The 5.4 mm by 4.4 mm device includes a 2.5 V reference and is built on a 2 /spl mu/m 10 V BiCMOS process and consumes 500 mW of power.

rief Papers A 12-b, 10-MHz, 250-mW CMOS A/D Converter

Abstract: A 12-b, 10-MHz, 250-mW, four-stage analog-to- digital converter (ADC) was implemented using a 0.8-pm p-well CMOS technology. The ADC based on a digitally calibrated mul- tiplying digital-to-analog converter (MDAC) selectively employs a binary-weighted capacitor array in the front-end stage and a unit-capacitor array in the remaining back-end stages to obtain 12 b level linearity while maintaining high yield. All the analog and digital circuit functional blocks are fully integrated on a single chip, which occupies a die area of 15 mm2 (4.2 mm x 3.6 mm). Measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the prototype are less than kO.8 LSB and H.8 LSB, respectively.

R/2R/sup +/ digital-analog converter (DAC)

Abstract: The most commonly used converter in digital-analog conversion is the one with an R/2R ladder circuit Accurate digital-analog converters (DAC) require extremely precise resistors Although the trimming procedure is used to adjust the desired resistors' ratio, aging and environmental factors affect the accuracy and linearity of a converter, thus introducing random conversion errors and reducing the converter's applicability With low precision resistors available, a new DAC design is proposed, based on a R/2R/sup +/ ladder circuit, where high converter precision is achieved due to better coverage of the analog range

Test and diagnosis of subranging A/D converters

Abstract: A test methodology for linear modeling of subranging analog-to-digital converters with digital correction is proposed. A reduced physical model of integral nonlinearity errors is obtained by the application of the ambiguity algorithm. Simulation results are provided which demonstrate that a sensible reduction of the number of test points can be obtained, thus reducing the high costs of testing, with low prediction errors.

A 10-bit 100 msamplesis bicmos d/a converter

Abstract: A 10-bit 100MSampleds current-steering D/A converter (DAC) has been designed and processed in a 0.8~ BiCMOS process. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR') at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5V, and has a power consumption of 650m W. The area of the chip-core is 2.2" x 2.2". The measured integral nonlinearity (INL) and differential nonlinearity (DNL) were both approximately 2 LSB. At a generated frequency off, = 0.3% (f, = 100 MSamplesh), the measured SFDR was approximately 43dB.

A 10-bit 100 MSamples/s BiCMOS D/A converter

Abstract: A 10-bit 100 MSamples/s current-steering D/A converter (DAC) has been designed and processed in a 0.8 /spl mu/m BiCMOS process. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR/sup 1/) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5 V, and has a power consumption of 650 mW. The area of the chip-core is 2.2 mm/spl times/2.2 mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) were both approximately 2 LSB. At a generated frequency of f/sub g//spl ap/0.3/spl middot/f/sub s/ (f/sub s/=100 MSamples/s), the measured SFDR was approximately 43 dB.

A practical implementation of dynamic testing of an AD converter

Abstract: This paper presents a practical testing system which can measure the dynamic parameters such as effective bits (EB), signal to noise ratio (SNR), differential and integral nonlinearity (DNL and INL) of an AD converter. For practical implementation we propose a mixed frequency estimation algorithm with weighted least square method to estimate the EB. Furthermore we combine the spectral average method with frequency domain estimation to measure the SNR and use the histogram method to calculate the DNL and the INL. For practical purpose, we choose a logical analyzer as the high speed data acquisition device and a PC as the instrument controller. Two programmable signal generators with very low harmonic distortion are used for signal source of the ADC Testing. All the instruments are controlled by the PC through GPIB with a test software. Finally we apply the proposed test system and algorithm to measure the dynamic parameters of a real ADC (Datel ADC-HS12B). Results show that the proposed test system and methods are fast and accurate. Users can test the ADC automatically without worrying about the expensive testing instruments, interface problems and complex algorithms which may occur in other ADC testing systems.

A high performance CMOS A/D converter for a digital camcorder system

Abstract: In a digital camcorder system, an A/D converter which converts the analog CCD (charge coupled device) signal into digital codes has an important role in determining the system performance. An A/D converter which has an 8-bit resolution and a 40 MSPS conversion speed is proposed. It has a ping-pong architecture. With 0.8 /spl mu/m double poly and double metal CMOS technology, the experimental prototype of the proposed A/D converter has a /spl plusmn/0.5 LSB integral nonlinearity error (INL) and /spl plusmn/0.5 LSB differential nonlinearity error (DNL).