Showing papers on "Loopback published in 2010"

Detailed Characterization of Transceiver Parameters Through Loop-Back-Based BiST

Abstract: The impact of impairments such as transmitter/receiver I/Q gain/phase mismatch on the performance have become severe due to high operational speeds and continuous technology scaling. In this paper, we present a built-in-self-test (BiST) solution for quadrature modulation transceiver circuits using only transmitter and receiver baseband signals for test analysis. The mapping between transmitter input signals and receiver output signals are used to extract impairment and nonlinearity parameters separately with the help of the NLS method and detailed nonlinear system modeling. Experimental measurement results are in good agreement with the simulations and they confirm the high accuracy of the proposed method.

Built-in Loopback Test for IC RF Transceivers

Abstract: The essentials of the on-chip loopback test for integrated RF transceivers are presented. The available on-chip baseband processor serves as a tester while the RF front-end is under test enabled by on-chip test attenuator and in some cases by an offset mixer, too. Various system-level tests, like bit error rate, error vector magnitude, or spectral measurements are discussed. By using this technique in mass production, the RF test equipment can be largely avoided and the test cost reduced. Different variants of the loopback setup including the bypassing technique and RF detectors to boost the chip testability are considered. The existing limitations and tradeoffs are discussed in terms of test feasibility, controllability, and observability versus the chip performance. The fault-oriented approach supported by sensitization technique is put in contrast to the functional test. Also the impact of production tolerances is addressed in terms of a simple statistical model and the detectability thresholds. This paper is based on the present and previous work of the authors, largely revised and upgraded to provide a comprehensive description of the on-chip loopback test. Simulation examples of practical communication transceivers such as WLAN and EDGE under test are also included.

Disk file preamplifier frequency-response and time delay compensation

Abstract: An apparatus including one or more reader circuits, one or more writer circuits, and a loopback channel. The one or more reader circuits may be configured to read data from a magnetic medium. The one or more writer circuits may be configured to write data to the magnetic medium. The loopback channel is coupled between the one or more reader circuits and the one or more writer circuits.

Method for detecting and automatically recovering Ethernet loopback

Abstract: The invention discloses a method for detecting and automatically recovering an Ethernet loopback, and relates to detection and recovery of the Ethernet loopback The method comprises the following steps: 1, completing initiation with a loopback detection initialization module; 2, constructing, transceiving and analyzing a loopback detection message to judge whether a loopback exists; 3, assigning a value to a flag, and redirecting the message to a CPU and sending a warning message if the loopback exists; 4, monitoring loopback failure recovery conditions and treating; and 5, repeating steps 2 to 4 The method for detecting and automatically recovering the Ethernet loopback can detect failures of loopbacks with one port or two ports, also can detect the loopback and judge that whether corresponding loopbacks are eliminated so as to recover the loopback, provides a solution for feint of loopback blockage caused by a loopback detection message counterfeited by a user, and has the characteristics of low requirement on hardware configuration of Ethernet switch chips and simple implementation

Calibration of quadrature imbalance via loopback phase shifts

Abstract: Apparatuses, systems, and methods for calibration of quadrature imbalance in direct conversion transceivers are contemplated. A transceiver controller may perform a self-calibration to address quadrature imbalance. The controller may isolate the transmitter and receiver from any antennas, couple the radio frequency (RF) section of the transmitter to the RF section of the receiver via a loopback path, and inject a calibration signal into the transmitter. In the loopback path, the controller may phase-shift the signal that propagates through the transmitter using two different phase angles to produce two different signals that propagate into the receiver. By measuring the two different signals that exit the receiver, the controller may be able to calculate correction coefficients, or parameters, which may be used to adjust elements that address or correct the quadrature imbalance for both the transmitter and receiver.

Calibration of quadrature imbalances using wideband signals

Abstract: Calibration of quadrature imbalance in direct conversion transceivers is contemplated. A transceiver controller may perform a self-calibration to address quadrature imbalance. The controller may couple the radio frequency (RF) section of the transmitter to the RF section of the receiver via a loopback path and transfer a wideband signal into the transmitter. In the loopback path, the controller may phase-shift the wideband signal that propagates through the transmitter using two different phase angles to produce two different signals that propagate into the receiver. By measuring the transmitter and receiver signals, and performing a Fast Fourier Transform calculation, the controller may be able to calculate correction coefficients, or parameters, which may be used to adjust elements that address or correct the quadrature imbalance for both the transmitter and receiver.

Recent Advances in Analog, Mixed-Signal, and RF Testing

Abstract: Due to the lack of widely applicable fault models, testing for analog, mixed-signal (AMS), and radio frequency (RF) circuits has been, and will continue to be, primarily based on checking their conformance to the specifications. However, with the higher level of integration and increased diversity of specifications for measurement, specification-based testing is becoming increasingly difficult and costly. As a result, design for testability (DfT), combined with automatic test stimuli generation, has gradually become a necessity to ensure test quality at an affordable cost. This paper provides an overview of cost-effective test techniques that either enhance circuit testability, or enable built-in self-test (BIST) for integrated AMS/RF frontends. In addition, we introduce several low-cost testing paradigms including the loopback testing, alternate testing, and digitally-assisted testing that offer the promise of significant test cost reduction with little or even no compromise in test quality. Moving forward, in addition to screening the defective parts, testing will play an increasingly important role in supporting other post-silicon quality assurance functions such as post-silicon validation, tuning, and in-field reliability of system chips.

Wireless local area network test system with forced transmit rates during protocol-based testing

Abstract: A system for performing wireless local area network testing of wireless devices may include a wireless local area network tester and a device under test. The tester and device under test may communicate over a wireless link. To ensure that the tester accurately analyzes test data, a data rate table is used that specifies fixed data transmission rates to be used by the device under test under both high-quality link conditions and low-quality link conditions. This forces the device under test to transmit control packets at the same high data rate during packet loopback testing, regardless of link quality. When the captured control packets are analyzed at the tester, both low-link-quality data and high-link-quality data may be analyzed using a common test template, ensuring accurate results.

Memory controller with loopback test interface

Abstract: In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

Optical access network, secondary network side termination node of an optical access network, and method for operating a network side termination node

Abstract: An optical access network has a first and a second network-side termination node, the first including a first transceiver arrangement connected to a first optical link, configured to send a first signal to a customer side termination node including a transceiver for receiving the first signal, and the second including a second transceiver arrangement connected to a second optical link and configured for sending a second signal to a transceiver of a customer-side termination node via the second link. The transceiver of the customer side termination node has a loopback element emitting a monitoring signal back to the network side termination nodes. Both network-side termination nodes have a link failure detector receiving the monitoring signal.

A novel MUX-FF circuit for low power and high speed serial link interfaces

Abstract: In this paper, a novel multiplexer-flip-flop (MUX-FF) topology using the current mode logic (CML) is presented. A CML multiplexer-latch (MUX-latch) is proposed by combining a multiplexer and the loopback storage part of a latch into a single module so that the buffer part of a latch can be removed. A MUX-FF is implemented by cascading two stages of MUX-latches. The output of a MUX-FF is edge-triggered, so it is insensitive to input noise. All the paths from inputs to the output are symmetric. Power and area can be reduced due to the removal of DFFs. Simulation results show that a MUX-FF can achieve a similar frequency as a conventional tree-type MUX by saving 56 % of area and 72 % of power consumption.

Stretching the limits of FPGA SerDes for enhanced ATE performance

Abstract: This paper describes a multi-gigahertz test module to enhance the performance capabilities of automated test equipment (ATE), such as high-speed signal generation, loopback testing, jitter injection, etc. The test module includes a core logic block consisting of a high-performance FPGA. It is designed to be compatible with existing ATE infrastructure; connecting to the device under test (DUT) via a device interface board (DIB). The core logic block controls the test module's functionality, thereby allowing it to operate independently of the ATE. Exploiting recent advances in FPGA SerDes, the test module is able to generate very high (multi-GHz) data rates at a relatively low cost. In this paper we demonstrate multiplexing logic to generate higher data rates (up to 10Gbps) and a low-jitter buffered loopback path to carry high speed signals from the DUT back to the DUT. The test module can generate 10Gbps signals with ~32ps (p-p) jitter, while the loopback path adds ~20ps (p-p) jitter to the input signal.

Digital frequency/phase locked loop

Abstract: A digital FLL/PLL is provided which is capable of converging an oscillation frequency from a VCO to a desired frequency at a high speed even without setting a damping factor corresponding to each VCO gain. A digital FLL/PLL of the present invention includes: a comparator for comparing a channel signal to a loopback signal having an oscillation frequency to generate a signal error; a digital loop filter for generating a control voltage that determines the oscillation frequency, on the basis of the signal error; a VCO for controlling an oscillation frequency on the basis of the control voltage; a loopback path through which the oscillation frequency generated by the VCO is outputted as the loopback signal to the comparator; and a control section for monitoring the signal error, and controlling the digital loop filter such that the oscillation frequency of the VCO becomes a stationary state, when detecting that the signal error meets a predetermined condition after the channel signal is switched.

Method and apparatus for testing an integrated circuit including an i/o interface

Abstract: Methods and apparatus provide for testing an integrated circuit including an input/output (I/O) interface. The method and apparatus place the I/O interface in a test mode by test enabling logic. During the test mode, the method and apparatus also provide, by a clock generator in the I/O interface, an internal phase-aligned receiver clock signal to a plurality of transceivers in the I/O interface. The clock generator is a transmitter portion of one of the plurality of transceivers in the I/O interface. The method and apparatus then monitor for errors in loopback data from the plurality of transceivers in the I/O interface by an automatic test equipment (ATE). The phase of the internal phase-aligned receiver clock signal is aligned with the loopback data of the plurality of transceivers, and the frequency of the internal phase-aligned receiver clock signal may be above about 200 MHz.

A method and testing backboard for single board production test

Abstract: The utility model discloses a method for single-chip board production test, wherein the single-chip board production test is realized by inserting the test single-chip board into a test backboard. Themethod comprises the steps that: the measured single-chip board produces an excitation signal, which is preferred to be a pseudo random binary sequence bit stream and is sent to the test backboard; the test backboard sends the excitation signal back to the measured single-chip board via a circuit interface loopback; the measured single-chip board checks the sent back excitation signal, and judgeswhether the measured single-chip board is normal according to the sent back excitation signal. Correspondingly, the utility model also provides a test backboard. Thereby, the utility model needs notto add the hardware cost to the measured single-chip board; the test cost is greatly reduced; the testing efficiency is improved; and the production test requirements needed by mass production are satisfied.

Novel BiST methods for parametric test in wireless transceivers

Abstract: This paper describes RF Built-in Self Test (BiST) techniques to test the performance of a RF CMOS integrated wireless transceiver using on-chip digital resources as both the stimuli and response analyzer. Using a defect-oriented approach, key RF blocks as well as the overall functionality and performance of the device are analyzed using a combination of block level and loopback testing. Using these methods, contributors to Error Vector Magnitude (EVM) such as amplifier gain, phase noise, and linearity performance (IP3) can be estimated and collected to predict the functional performance of a Digital Radio Processor (DRP) for wireless applications.

Mimo channel loopback

Abstract: A method and apparatus for efficiently providing a large volume of channel feedback, e.g.. for OFDM MISO and MIMO systems, is described herein. To that end, a mapping unit in an OFDM transceiver maps channel feedback values, e.g., received reference signal values or channel estimates derived therefrom, on a one-to-one basis to individual transmission subchannels. More particularly, the mapping unit maps a feedback value, e.g., the received reference value or a channel estimate derived therefrom, to a single transmission subchannel of an outgoing OFDM signal. For example, the mapping unit may map the feedback value to an input of a frequency transform unit, such as an inverse discrete Fourier transform unit, to map the feedback value to a single transmission subchannel comprising an OFDM transmission subcarrier. The OFDM transceiver transmits the outgoing OFDM signal to the remote transceiver to provide the feedback value to the remote transceiver.

Method and equipment for detection processing of loopback of aggregation link

Abstract: The invention discloses a method and equipment for detection processing of loopback of an aggregation link. The method comprises the following steps: sending a identifier carrying the aggregation link from each member port in the aggregation link and a first loopback detection message of the identifier of the member port for sending the first loopback detection message; receiving the identifier carrying the aggregation link at the each member port in the aggregation link and a second loopback detection message of the identifier of the member port for sending the second loopback detection message; and determining whether to form a loop or not according to the identifiers of the aggregation links in the first loopback detection message and the second loopback detection message. The method and the equipment can timely process the loopback detection processing problem in the data communication equipment.

Accelerating Test, Validation and Debug of High Speed Serial Interfaces

Abstract: High-Speed Serial Interface (HSSI) devices have become widespread in communications, from the embedded to high-performance computing systems, and from on-chip to a wide haul. Testing of HSSIs has been a challenging topic because of signal integrity issues, long test time and the need of expensive instruments. Accelerating Test, Validation and Debug of High Speed Serial Interfaces provides innovative test and debug approaches and detailed instructions on how to arrive to practical test of modern high-speed interfaces.Accelerating Test, Validation and Debug of High Speed Serial Interfaces first proposes a new algorithm that enables us to perform receiver test more than 1000 times faster. Then an under-sampling based transmitter test scheme is presented. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100ms, while the test usually takes seconds. The book also presents and external loopback-based testing scheme, where and FPGA-based BER tester and a novel jitter injection technique are proposed. These schemes can be applied to validate, test and debug HSSIs with data rate up to 12.5Gbps at a lower test cost than pure ATE solutions. In addition, the book introduces an efficieng scheme to implement high performance Gaussian noise generators, suitable for evaluating BER performance under noise conditions.

Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits

Abstract: A traditional specification-based core-level test method is no longer attractive in testing deeply embedded analog and mixed-signal circuits due to limited accessibility and resource issues. In order to overcome such difficulties, loopback testing has been considered as a promising solution when circuits include data conversion units; however its widespread adoption has been hindered due to fault masking, which may cause serious yield loss and test escape. The combination of seriously degraded components in a signal path and overqualified components in another signal path, may result in the overall performance of the loopback path being completely fault-free. This paper presents an efficient loopback test methodology which provides test accuracy equivalent to a traditional specification-based test. In our approach, a traditional loopback scheme is re-configured with an analog filter and an adder implemented on a Device Interface Board (DIB), and a multiple tone input is applied to the DUTs. The outcome of the proposed test is a set of performance parameters, allowing the evaluation of DUTs with respect to its specification, and efficient guidance of a self-repair mechanism. The mathematical analysis for the fault masking problem, based on linearity and noise parameters, is provided. In addition, various design parameters which may impact the accuracy of the proposed method are investigated. Both simulation and hardware measurements are presented to validate the proposed technique.

SDH (Synchronous Digital Hierarchy) multi-domain comprehensive test device and test method thereof

Abstract: The invention discloses an SDH (Synchronous Digital Hierarchy) multi-domain comprehensive test device and a test method thereof, mainly solving the problem that single test equipment tests the network performance of an ATM (Asynchronous Transfer Mode) network transmitting in an SDH mode or an IP (Internet Protocol) packet network packed by adopting an HDLC (High level Data Link Control) protocol.The SDH multi-domain comprehensive test device mainly comprises a test data processor, an SDH processor and a microcomputer control system. The test method comprises the following steps of: (1) initializing the working mode of the SDH multi-domain comprehensive test device; (2) generating test information cells or packets of the corresponding working mode by the test data processor, mapping into an SDH frame and sending to a tested network element by the SDH processor; (3) extracting the test information cells or the packets from the loopback SDH frame by the SDH processor; (4) processing thereceived test information cells or packets by the test data processor; and (5) analyzing and displaying a test result by the microcomputer control system. The invention can not only test a single-mode or multi-mode multi-rate SDH network, but also realize that the single equipment tests the network performance of the ATM network and the packet network, and has easy and convenient operation and high cost performance.

Simulation of LTE Signaling

Abstract: This article aims to present a simulation and emulation software that was developed to simulate the call flows of a LTE (Long Term Evolution) network. LTE is the latest Mobile Telecommunications technology being currently in development and testing phase. The simulator can be used as an e-Learning software, for teaching the procedures and phases of different LTE scenarios. Call flows can be visualized trough the simulation panel, where signaling messages can be run continuously or step-by-step, for the purpose of detailed analysis. The simulator has the capability to generate real signaling packets, that are being sent to a virtual loopback adapter and captured / dissected using the Wireshark software. In this way a whole simulation environment is created that is very useful for teaching the latest mobile telecommunications technology, the LTE (Long Term Evolution) system.

Transmitter-only ic chip having external loopback test function and external loopback test method using the same

Abstract: A transmitter-only integrated circuit (IC) chip for performing an external loopback test without an additional receive pin in a chip and an external loopback test method include drivers, mounted on the transmitter-only IC chip, for transmitting data through transmit pads that are installed in correspondence to a plurality of channels; and a loopback test circuit for receiving data as external loopback data through one of the transmit pads set as a receive pad for a test, the data being transmitted through one of the remaining transmit pads, and then comparing the received external loopback data with original transmit data.

Ethernet port loopback detection method and multi-service transport platform

Abstract: The invention discloses an Ethernet port loopback detection method and a multi-service transport platform. The multi-service transport platform comprises a receiving unit used for receiving a data frame which carries a source MAC address, a storage unit used for storing an address forwarding table, and a detection unit used for looking up the address forwarding table, and determining a port generates data frame loopback when detecting the source MAC address is in the address forwarding table and a receiving port is different from a corresponding port in the address forwarding table. The method and the multi-service transport platform have the advantages of effectively detecting the Ethernet port generating the loopback so as to avoid the oscillation of an MAC address caused by the loopback of the Ethernet port of MSTP equipment and ensuring service security and normalcy.

Two-way serial communication protocol based communication method for fire alarm system

Abstract: The invention discloses a two-way serial communication protocol based communication method for a fire alarm system, wherein the fire alarm system comprises a controller, a plurality of loop cards connected with the controller in a matched way or a communication circuit connected with the controller, and a plurality of fire communication terminals; and the communication frames of the transceiving information between the controller and the fire communication terminals comprise loopback information comprising 1 type-bit datum, 8 address-bit data, a plurality of control-bit data, 1 odd/even checkbit datum from the fornt to back and a plurality of PW pulses and a synchronizing signal. The communication method comprises following steps of information sending, information transfer, information receiving, analyzing and judging and information replay. The invention has novel and reasonable design, good use effect and high intellectualization degree and can simply, conveniently, timely and accurately transfer the information to the fire communication terminals, thereby realizing the real-time two-way communication between the controller and the control terminals of the fire alarm system and having quick communication speed and accurate data transmission.

Message forwarding method and switching chip

Abstract: The invention discloses a message forwarding method. The method comprises the following steps of: configuring a cascade port of a switching chip into an internal self-loop mode; performing termination process on a message; looping back the message after the termination process at the cascade port; and initializing the loopback message and forwarding the message. The invention also provides the switching chip. According to the technical scheme of the invention, the message forwarding in MPLS VPN along an uplink direction and a downlink direction can be realized by using one PE and one port.

Communication system, communication apparatus, and communication method

Abstract: PROBLEM TO BE SOLVED: To provide a communication system, communication apparatuses and a communication method, wherein, each communication apparatus is bus-connected separately to two communication lines different from each other, the each communication apparatus is connected separately with two communication apparatuses in one to one manner to form a loop connection, thereby forming a flexible configuration achieving high speed and failure resistance even when the configuration uses existing protocols SOLUTION: The respective communication apparatuses 1, 2a have different connection sections, respectively, are bus-connected separately to the communication lines 3a, 3b, 3e, and when one of the communication apparatuses breaks down and so on, the connection section which has become incommunicable is replaced by a loopback section COPYRIGHT: (C)2011,JPO&INPIT

Method, device and system for local exchange

Abstract: The embodiment of the invention discloses a method, a device and a system for local exchange, relating the technical field of communication. The invention is designed for solving the problem that different services can not be treat differentially according to the existing technology, so that different processing modes are employed. The method comprises the following steps: confirming current service type of both communicating sides when the both communicating sides are within the signal coverage area of a same base station controller; transmitting local loopback establish indication information to the base station controller, wherein the information carries a loopback identification. The embodiment of the invention details the local connection function to the service level and is more suitable for control and management of local area connection by the network.

Method for measuring qos of voip network

Abstract: PURPOSE: A method for measuring the QoS of a VoIP network is provided to measure the quality of a VoIP network through a fixed algorithm. CONSTITUTION: A VoIP network quality measuring server checks the sequence number and time stamp of RTP packets(S205). The VoIP network quality measuring server measures VoIP network quality in an upstream connection(S206). The VoIP network quality measuring server measures the entire loopback VoIP network quality based on the sequence number and time stamp recorded in payload regions of the RTP packets. The VoIP network quality measuring server extracts the correlation between the measured entire loopback VoIP network quality and the VoIP network quality. The VoIP network quality measuring server measures VoIP network quality in a downstream connection.

Method, device and system for evaluating network quality

Abstract: The invention discloses a method, a device and a system for evaluating network quality. The method comprises the following steps of: enabling the function of MPLS VPN in a network, and opening two test VPNs: VPN1 and VPN2; arranging a detector only on a source node of the network, and enabling the loopback function of MPLS VPN on a target node which is not provided with the detector; planning routers of VPN1 and VPN2 of each node, and making each node save a router table of VPN1 and VPN2 per se; forwarding an initial testing stream emitted by the detector to a target node by the source node, and performing loopback on a final testing stream to the source node by the target node; and providing the final testing stream for an acquisition analysis center by the source node, and analyzing the final testing stream and the pre-stored initial testing stream and utilizing the analysis data to evaluate the network quality by the acquisition analysis center. The method has the advantages of strong expandability, simple management and low cost.