Showing papers on "Metal gate published in 1993"

Thin-film transistor and a liquid crystal matrix display device using thin-film transistors of this type

Abstract: A thin-film transistor comprises a gate electrode formed on a glass substrate, a gate insulating film formed essentially over an entire surface of the substrate to cover the gate electrode, a non-single-crystal silicon semiconductor film placed on the gate insulating film to cover the gate electrode; and a drain electrode and a source electrode spaced a specified distance apart on the semiconductor film and electrically connected to the semiconductor film so as to form the channel region of the transistor. The gate electrode is made of titanium-containing aluminum.

Low resistance device element and interconnection structure

Abstract: A composite semiconductor structure which replaces polysilicon for conductive device elements and provides lower resistance interconnections between devices. The preferred structure is a conductive adhesion layer deposited in place of polysilicon in contact with a conductive metal layer traversing the interconnection. The preferred material for the adhesion layer is tungsten nitride, and for the metal layer--tungsten. If polysilicon is retained for device elements, the adhesion and metal layers may be placed in contact with the polysilicon element and along the interconnect structure providing an interconnect with lower resistance. Increased adhesion may be obtained by adding a cap layer of dielectric material atop the metal layer.

Fabricating dual gate thin film transistors

Abstract: A method for fabricating a dual gate thin film transistor using a power MOSFET process having a first gate area (22) made from a monocrystalline silicon. A dielectric layer (25) is formed over the monocrystalline silicon. A first gate electrode (58) contacts the first gate area (22). A thin film transistor is fabricated on a first island of polysilicon (29) over the dielectric layer (25). The thin film transistor has a second gate electrode (55), and drain and source electrodes (56, 57) wherein the drain and source electrodes (56, 57) contact different portions of the first island of polysilicon (29). Preferably, the first gate electrode (58) is coupled to the second gate electrode (55).

Thin film transistor having a lightly doped drain and an offset structure for suppressing the leakage current

Abstract: A thin film transistor wherein generation of a leakage current is prevented to improve the operation stability thereof and a method for manufacturing the same. A polysilicon layer is formed on an insulating layer. A gate insulating layer is formed on the polysilicon layer. A gate electrode having a barrier layer formed thereon is formed on the gate insulating layer. The sidewall surface portion of the gate electrode is anodic oxidized to form a metal oxide layer on the sidewall of the gate electrode. A lightly doped drain region having a lower impurity concentration than that of source and drain regions of the thin film transistor or an offset region wherein no impurity is doped is formed in a portion of the polysilicon layer under the metal oxide layer. The thin film transistor may be manufactured by a low temperature process, and leakage current is suppressed when a reverse bias voltage is applied. Therefore, the operation stability of the thin film transistor is improved.

A mos transistor having a composite gate electrode and method of fabrication

Abstract: A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.

Method of fabricating a semiconductor device with raised diffusions and isolation

Abstract: A method of forming a MOS FET in which the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The sidewalls that are used to form an LDD source and drain separate a gate contact from source and drain contacts.

Method of making a self-aligned dual-bit split gate (DSG) flash EEPROM cell

Abstract: A method of making an EEPROM cell structure which includes two floating gate transistors separated by a select gate transistor with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor. The floating gates of the two transistors are formed from a first polysilicon layer, the control gates of the two transistors are formed from a second polysilicon layer, and the select gate is formed from a third doped polysilicon layer. The channel length of the select gate transistor is fully self-aligned to the floating gate transistors. A word line is formed over the control gates and forms the select gate. The word line runs generally perpendicular to bit lines which contact the drain regions of the two floating gate transistors. Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure.

Sixteen megabit static random access memory (SRAM) cell

Abstract: A new and improved static random access memory (SRAM) cell wherein separate regions of polysilicon are formed over a silicon substrate and are separated by defined openings therein into which oxide filler material is introduced to render the regions of polysilicon and oxide substantially co-planar at their upper surfaces. An access transistor and a thin film load transistor are formed within and adjacent to first and second regions of the polysilicon, respectively, and yet a third, pull down transistor is formed within and adjacent to a third polysilicon region. The thin film transistor includes a thin second layer of polysilicon which is electrically isolated from the second one of the polysilicon regions and is doped to form therein source, drain and channel regions. Advantageously, the thin film transistor is formed on this substantially planar surface, thereby improving process yields and device performance. In a preferred embodiment of the invention, a thick oxide layer is formed and retained over the upper surface of the access transistor, and the thin second layer of polysilicon is extended over this thick oxide layer where it is connectable to a source of supply voltage. In this manner, the thick oxide layer operates to capacitively decouple the access transistor from the supply voltage. Also in a preferred embodiment of the invention, the second layer of polysilicon is extended over the substantially co-planar surfaces described above and into contact with the third polysilicon region to establish an electrical connection between the thin film transistor drain and the pull down transistor gate. Also in a preferred embodiment of the invention, the second polysilicon region includes a buried contact to the silicon substrate which establishes a circuit node for the SRAM cell electrically joining a pull down transistor gate, a pull down transistor drain, and thin film transistor gate, and an access transistor drain.

Method of producing semiconductor devices of a MONOS type

Abstract: A method of producing a semiconductor device of the type which includes a semiconductor substrate; a gate insulating layer of a triplex structure formed on the semiconductor substrate and composed of a first oxide layer, an oxidation-resistant layer and a second oxide layer, and a gate electrode formed on the gate insulating layer, includes the steps of: forming the first oxide layer, the oxidation-resistant layer, and the second oxide layer successively on the semiconductor substrate; adjusting the thickness of the oxidation-resistant layer during or after the formation thereof in such a way that the entire oxidation-resistant layer can be oxidized in a post-process in which the oxidation-resistant layer is oxidized except for that region which corresponds to the gate electrode; and oxidizing the oxidation-resistant layer except for the region corresponding to the gate electrode and forming an oxide layer around the gate electrode, whereby the oxidation-resistant layer is entirely oxidized except for the region corresponding to the gate electrode. The resulting silicon oxide layer can be used as an address gate or as the gate insulating layer of an MOS transistor gate for a peripheral circuit.

Method of preventing fluorine-induced gate oxide degradation in WSix polycide structure

Abstract: A new method of fabricating a polycide gate structure is described A gate polysilicon layer is provided overlying a gate oxide layer on the surface of a semiconductor substrate A thin conducting diffusion barrier layer is deposited overlying the gate polysilicon layer A layer of tungsten silicide is deposited overlying the thin conducting diffusion barrier layer wherein a reaction gas used in the deposition contains fluorine atoms and wherein the fluorine atoms are incorporated into the tungsten silicide layer The gate polysilicon, thin conducting diffusion barrier, and tungsten silicide layers are patterned to form the polycide gate structures The wafer is annealed to complete formation of the polycide gate structures wherein the number of fluorine atoms from the tungsten silicide layer diffusing into the gate polysilicon layer are minimized by the presence of the thin conducting diffusion barrier layer and wherein because the diffusion of the fluorine atoms is minimized, the thickness of the gate oxide layer does not increase This prevents the device from degradation such as threshold voltage shift and saturation current decrease

Method of fabricating semiconductor gate electrode with fluorine migration barrier

Abstract: A PMOS device is provided having a diffusion barrier placed within a polysilicon gate material. The diffusion barrier is purposefully implanted to a deeper depth within the gate material than subsequently placed impurity dopants. The barrier comprises Ar atoms placed in fairly close proximity to one another within the gate conductor, and the impurity dopant comprises ions of BF2. F from the impurity dopant of BF2 is prevented from diffusing to underlying silicon-oxide bonds residing within the oxide bulk. By minimizing F migration to the bond sites, the present polysilicon barrier and method of manufacture can minimize oxygen dislodgment and recombination at the interface regions between the polysilicon and the gate oxide as well as between the gate oxide and silicon substrate.

Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip

Abstract: A semiconductor device having high and low voltage transistors on the same chip. High voltage NMOS transistor 76 comprises a polysilicon gate 40 doped at first dopant level. Low voltage NMOS transistor comprises a polysilicon gate 44 doped at a second dopant level. The second dopant level is higher than the first. High voltage PMOS transistor 84 comprises a polysilicon gate 48 doped at a third dopant level. Low voltage PMOS transistor comprises a polysilicon gate 52 doped at a fourth dopant level. The fourth dopant level is higher than the third.

Fabrication method for III-V heterostructure field-effect transistors

Abstract: A heterojunction device, and a method for producing the device. A gate air bridge is formed at the mesa sidewall between the active region and the gate bonding pad to lower the gate leakage current. The device has a double recessed gate to reduce local fields in the vicinity of the gate. The fabrication method uses dielectric intermediate and final passivation layers to optimize the double-recess profile and control the extension of the high-field region between the gate and the drain. This combination increases the breakdown potential of the device, but minimizes the effective gate length of the device, preserving high frequency performance.

Method of fabricating a high voltage MOS transistor for flash EEPROM applications having a uni-sided lightly doped grain

Abstract: High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide isolation structures are formed as in the prior art. A sacrificial thermal oxide layer simultaneously removes Kooi effect residual nitridization and provides gate oxide for the high voltage transistors of a thickness commensurate with the high voltage application. The sacrificial oxide is thereafter removed from all circuit areas except over high voltage device active areas. Growth of tunnel oxide, first polysilicon, interpoly dielectric, peripheral gate oxide and second polysilicon layers as well as patterning of the layers are accomplished in a known manner. The second polysilicon layer is patterned to create lines which lie within lines formed of the first polysilicon layer, the second polysilicon layer aiding controlling the final channel length of the high voltage devices. A uni-sided lightly doped drain structure is created in n-channel enhancement and intrinsic high voltage devices only by an appropriately shaped mask to block the n+ source-drain implant over a previously implanted tip region disposed between the gate and drain, thereby minimizing hot-carrier effects in the drains. Metallization for the high voltage transistors is made over field oxide to the polysilicon control gates formed from the first polysilicon layer.

Constant current generating circuit for semiconductor devices

Abstract: The constant current generating circuit includes a high resistance element for generating a very small current. This very small current is supplied to a first MOS transistor having a sufficiently large gate width to gate length ratio. The gate-source voltage of the first MOS transistor becomes its threshold voltage VTH, and the voltage applied across a resistance connected between the gate of the first MOS transistor and the ground line is set to a constant value VTH. Thus, a constant current is normally passed through the resistance. Since the very small current is supplied from the high resistance element which is normally turned on, regardless of the change of the power supply voltage, a constant current can be generated stably.

Multilayer polysilicon gate self-align process for VLSI CMOS device

Abstract: A new method of forming a self-aligning polysilicon gate is described. A gate silicon oxide is formed over a silicon substrate. A polysilicon layer is formed over the gate oxide. A native silicon oxide layer is formed over the polysilicon layer. A second polysilicon layer is formed over the native silicon oxide layer. Additional alternating layers of polysilicon and native silicon oxide are formed as desired. The wafer is annealed at between about 800° to 1000° C. This causes, it is believed, the silicon oxide gas from the multiple native silicon oxide layers to be exhausted resulting in the removal of all silicon oxide layers. A polycide layer is formed overlying the multiple polysilicon layers, if desired. Conventional lithography and etching techniques are used to form a gate. Ions are implanted into the substrate to form source/drain regions, using the multilayer gate as a mask. Rapid thermal annealing activates the impurities. A dielectric layer is deposited followed by conventional metallization techniques to complete construction of the integrated circuit.

Impact of polysilicon depletion in thin oxide MOS technology

Abstract: Accurate characterization of thin oxide conduction current, breakdown, and MOSFET current require an accounting for the voltage drop due to the depletion of the polysilicon gate. The reduction of oxide thickness and polysilicon doping ascerbate this effect. Scaled n+/p+ dual gate CMOS technology incorporates both these trends, due to process integration constraints which limit the concentration of active dopants in polysilicon. The authors investigate effects of polysilicon depletion on the thin oxide MOS system. >

Method of making a non-volatile floating gate memory device with peripheral transistor

Abstract: The present invention discloses a non-volatile memory device having a multi-level gate structure. The storage cell transistor in the cell array region and the transistor in the peripheral circuit region have the same multi-level gate structure. Also, multi-level polycrystalline silicon layers in the peripheral circuit region are connected to each other, and thus utilized as an electrically singular gate electrode. The gate structures of the two regions are formed through a single etching process, so that the decreased processing number of photolithography simplifies overall process, and reduces the damage on the field oxide layer to thereby enhance an insulating performance.

Method for forming semiconductor device comprising metal oxide

Abstract: An insulated gate field effect semiconductor device comprising a substrate having provided thereon a thin-film structured insulated gate field effect semiconductor device, said device being characterized by that it comprises a metal gate electrode and at least the side thereof is coated with an oxide of the metal. The insulated gate field effect semiconductor device according to the present invention is also characterized by that the contact holes for the extracting contacts of the source and drain regions are provided at about the same position of the end face of the anodically oxidized film established at the side of the gate. Furthermore, the present invention provides a method for forming insulated gate field effect semiconductor devices using less masks.

DRAM cell having raised source, drain and isolation

Abstract: A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain form a self-aligned aperture for a surface strap that insulates the strap from misaligned portions of the gate stack.

Planarization of a gate electrode for improved gate patterning over non-planar active area isolation

Abstract: The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.

Method for programming a semiconductor memory device

Abstract: A programmable EEPROM cell structure consisting in a split-gate structure in series with a coupling capacitor between the floating gate and an additional program gate in order to provide enhanced injection efficiency. The electron injection is controlled by a control gate at the source side. The area of the coupling capacitor is selected with a substantial coupling factor to a high voltage onto the floating gate during programming so as to produce hot-electron injection at the split point in the channel region between the control gate and the floating gate. Submicrosecond programming at a 5 V drain voltage can thereby be achieved.

MOS poly-si thin film transistor with a flattened channel interface and method of producing same

Abstract: A thin film field effect transistor has a three-layer structure including a polycrystalline semiconductor layer to be a channel region, a conductive layer to be a gate electrode and a insulating layer to be a gate insulating film between the channel region and the gate electrode. The roughness of an interface between the channel region and the gate insulating film is less than a few nm so that the current drivability of the transistor is improved.

Method of making thin film transistors

Abstract: A method of making thin film transistors such that the first conductive layer of a thin film transistor is formed with an aluminum system metal having a low electric resistance, and another metal capable of anodic oxidation is deposited to prevent the aluminum system metal from producing hillocks. The metal capable of anodic oxidation and part of the aluminum system metal are changed into an insulator by an anodic oxidation treatment. In all, the gate insulator of the thin film transistor comprises three layers of aluminum oxide, an oxide of the metal capable of anodic oxidation, and silicon nitride. The method makes it possible to form the lower-layer wiring and gate electrode having a low electric resistance and a flawless gate insulator having excellent insulative quality.

Method of making a thin film transistor

Abstract: This is a method of fabricating a transistor on a wafer. The method comprises: forming a doped silicon layer; patterning the active transistor regions of the doped silicon layer and utilizing a silicon etch to remove the non-transistor regions of the doped silicon layer to create a silicon mesa; forming a gate oxide layer on a doped silicon mesa; depositing a polysilicon layer on top of the oxide layer; depositing a photoresist layer over the polysilicon mesa; patterning the photoresist layer with a gate configuration; etching to remove portions of the polysilicon layer using the photoresist as a mask to create a polysilicon gate; depositing a TEOS layer over the polysilicon gate and exposed gate oxide; etching to remove portions of the TEOS layer and the exposed gate oxide to leave sidewall spacers on sides of the polysilicon gate and sides of silicon mesa; depositing a metal layer over remaining portions of the polysilicon gate, the sidewall spacers, and the silicon mesa; annealing the wafer to react portions of the metal layer with exposed portions of the silicon mesa to form a metal silicide; etching all unreacted the metal layer to leave the silicided portions of the polysilicon gate and silicided portion of the doped silicon layer.

Method for forming a DRAM trench cell capacitor having a strap connection

Abstract: A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain combine with nitride sidewalls on a gate contact aperture to separate a gate contact from source and drain contacts.

Process for fabricating a MOS device having protection against electrostatic discharge

Abstract: A MOS device having protection against electrostatic discharge includes a protection diode formed below the MOS device so that excess charge buildup in the MOS device is conducted away from the MOS device by the protection diode.

Non-volatile large capacity high speed memory with electron injection from a source into a floating gate

Abstract: A non-volatile semiconductor memory providing a semiconductor substrate, drain and source regions which are provided on the surface of the semiconductor substrate and have a conductivity type different from that of the semiconductor substrate, a channel region formed between the drain and source regions, a floating gate (first gate electrode) for covering a part of the channel region. The drain region is self-aligned with the floating gate, and the source region is offset from the floating gate through an offset region by a constant distance. As a result, the drain and source regions are located asymmetrically with respect to the floating gate. A control gate (second gate electrode) substantially controls the surface potentials on the underside and in the vicinity of the floating gate. A selection gate (third gate electrode) controls the surface potential of the whole channel region including the offset region. The control gate as the second gate electrode is directly capacitively-coupled with the floating gate wholly (or partially) in portions other than the offset region. The selection gate is the third gate electrode is provided above the control gate and the floating gate so as to overlap with the control gate over all of the channel region, whereby electrons are injected from the source region to permit electrical writing and erasure.

Electrically programmable memory cell

Abstract: An EPROM cell comprises an MOS device including a floating gate electrode (44, 64) overlying, and ohmically insulated from, the channel region (26) of the MOS device, and a separate diode (18) including a p-n junction (54) having a substrate surface intercept (30). A floating gate electrode (64) overlies the diode p-n junction intercept (54) and is ohmically isolated therefrom by an intervening insulating layer. Writing of data into the floating gate electrode of the MOS device is achieved by causing a voltage breakdown across the diode p-n junction (54) and the flow of high energy electrons across the junction. A voltage is simultaneously applied to the diode gate electrode (64) thereby attracting some of the high energy electrons through the overlying insulating layer into the diode floating gate electrode. The diode gate electrode (64) is ohmically connected to the MOS floating gate electrode (44) on which some of the electrons are stored for affecting the turn-on, turn-off, characteristics of the MOS device.

Method of making a self aligned static induction transistor.

Abstract: A method of fabricating self aligned static induction transistors. The method comprises fabricating an N silicon on N⁻ silicon substrate having an active area. A guard ring is formed around the active area. An N⁺ polysilicon layer is formed that comprises source and gate regions. An oxide layer is formed on the N⁺ polysilicon layer. A second polysilicon layer is formed on the oxide layer. A second oxide layer is formed on the second polysilicon layer which is then masked by a self aligning mask. Trenches are etched into the substrate using the self aligning mask and gate regions are formed at the bottom of the trenches. A first layer of metal (gate metal) is deposited to make contact with the gate regions. A layer of photoresist is deposited and planarized, and the first layer of metal is overetched below the top surface of the trench. Plasma nitride is deposited and planarized, and a polysilicon mask is deposited over the planarized layer of plasma nitride. The polysilicon mask is etched to expose the gate metal disposed on the field. A second layer of metal is deposited to make contact with the source and gate regions. A passivation layer is formed, and interconnection pads are formed that connect the first and second layers of metal. The present method employs a single minimum geometry trench mask. The key features of the transistor are defined by the trench mask and related processing parameters. Because of the self alignment achieved by the present invention, the number of channels per unit area is higher, which results in higher transconductance. In addition, some of the parasitic capacitance is eliminated by the present invention, resulting in faster operational speed. The variable sidewall trench oxide thickness allows fabrication of static induction transistors with higher or lower breakdown voltages according to the thickness that is chosen, and for a more graded P gate junction.