Showing papers on "Multistage interconnection networks published in 1988"

High-performance multi-queue buffers for VLSI communications switches

Abstract: Small nxn switches are key components of multistage interconnection networks used in multiprocessors as well as in the communication coprocessors used in multicomputers. The design of the internal buffers in these switches is of critical importance for achieving high throughput low latency communication. We discuss several buffer structures and compare them in terms of implementation complexity and their ability to deal with variations in traffic patterns and message lengths. We present a new design of buffers that provide non-FIFO message handling and efficient storage allocation for variable size packets through the use of linked lists managed by a simple on-chip controller. We evaluate the new buffer design by comparing it to several alternative designs in the context of a multi-stage interconnection network. Our modeling and simulations show that the new buffer outperforms its “competition” and can thus be used to improve the performance of a wide variety of systems currently using less efficient buffers.

The distribution of waiting times in clocked multistage interconnection networks

Abstract: Analyzes the random delay experienced by a message traversing a buffered, multistage packet-switching banyan network. The authors find the generating function for the distribution of waiting time at the first stage of the network for a very general class of traffic, assuming messages have discrete sizes. For example, traffic can be uniform or nonuniform, messages can have different sizes, and messages can arrive in batches. For light-to-moderate loads, the authors conjecture that delays experienced at the various stages of the network are nearly the same and are nearly independent. This allows us to approximate the total delay distribution. Better approximations for the distribution of waiting times at later stages of the network are attained by assuming that in the limit a sort of spatial steady state is achieved. Extensive simulations confirm the formulas and conjectures. >

Realizing fault-tolerant interconnection networks via chaining

Abstract: A scheme applicable to a wide class of multistage interconnection networks to enhance their fault-tolerant capability is proposed. Multiple paths between each input-output pair of a network are created by connecting switching elements within the same stage. This scheme provides a network with alternative paths at every stage, requires a simple self-routing algorithm, and allows a network to become more robust as its size increases. An analysis is performed to obtain a quantitative measurement of the reliability improvement of the scheme. >

Performance analysis of multiple bus interconnection networks with hierarchical requesting model

Abstract: The authors study the performance of multiprocessor systems employing multiple buses as the interconnection networks under a nonuniform requesting model, called the hierarchical requesting model. The effective memory bandwidth is chosen as the performance measure. The networks investigated include multiple bus networks with full bus-memory connection, multiple bus networks with single bus-memory connection, and multiple bus networks with partial bus-memory connection. The authors also propose a type of multiple bus network with partial bus-memory connection, called partial bus networks with K classes. The N costs and fault-tolerant capabilities of the multiple bus networks are also evaluated and compared to one another. It is shown that the partial bus networks with K classes are useful in applications requiring high performance and degree of fault tolerance with moderate cost. >

Optical multistage interconnection networks for large-scale multiprocessor systems

Abstract: In numerical computing systems with a tightly coupled large-scale multiprocessor architecture (MIMD or multiple SIMD), the interconnection network among the system elements is of considerable importance. Such a network may be built by nodes and channels made with optical components presently available. In this work two types of optical reversible node are discussed: the symmetrical exchange box and the complete node, and two examples of optical interconnection networks of the multistage nonblocking type are considered: two-sided, based on the symmetrical interchange box, and one-sided, based on the complete node. These networks may be used either in digital optical computer architectures or in traditional multiprocessor systems and may function both in guided transmission and free transmission of optical information.

Extra Group Network: a cost-effective fault-tolerant multistage interconnection network

Abstract: This paper introduces a new class of fault-tolerant multistage interconnection networks, dubbed as Extra Group Networks (EGNs). An EGN-m of size N is designed to have m + 1 unique path multistage networks of size N/m. This approach of constructing the network allows that an EGN-m can provide “full access” capability in the presence of multiple faults, up to m, in any stage. EGNs can also maintain the permutation capability of the unique path multistage network of size N in the presence of any single fault. We show that EGNs are most cost-effective than other previously proposed fault-tolerant multistage interconnection networks with a similar fault-tolerant capability.

Fault tolerance capabilities in multistage network-based multicomputer systems

Abstract: The inherent fault tolerances of systems based on nonredundant multistage interconnection networks (MINs) is investigated. Graph models are used to describe the system, indicate faults, study their effects, and aid in mathematical formulation of these effects. Methodical terminology for defining functionality of two-sided-MIN-based multicomputer systems and specifying their fault tolerance of such systems is analyzed. The effects of a single faulty vertex and a single faulty edge are studied, and single fault tolerance, with respect to various definitions of system functionality, is evaluated. Multiple faults are analyzed. A practical example of the banyan network used in the Texas reconfigurable array computer (TRAC) and its fault tolerance capabilities are given. >

A distributed resource management mechanism for a partitionable multiprocessor system

Abstract: A resource-management mechanism is presented for a multiprocessor system consisting of a pool of homogeneous processing elements interconnected by multistage networks. The mechanism aims at making effective use of hardware resources of the multiprocessor system in support of high-performance parallel computations. It can create many physically independent subsystems simultaneously without incurring internal fragmentation,. Each subsystem can configure itself to form a desired topology for matching the structure of the parallel computation. The mechanism is distributed in nature; it is divided into three functionally disjoint procedures that can reside in different loci for handling various resource-management tasks concurrently. Simulation results show that, by eliminating internal fragmentation, the mechanism achieves better source utilization than a reference machine. >

Switching method for multistage interconnection networks with hot spot traffic

Abstract: A method of switching data packets through a multistage interconnection network (MIN), to prevent hot spot traffic from degrading uniform traffic performance. Each of the address bits in each packet determine the output link at each particular stage of the network to which the packet must be routed. A packet is accepted at an input buffer of the stage only if an acceptance test is met. This acceptance test depends not only on the availability of a buffer at the input buffer at a stage of the network, but also on how the address bits of the packet are related to address bits of other packets in the buffer, and on the stage of the network. If the acceptance test is not met, the packet is retained in the previous stage of the MIN, and is moved to the rear of a queue of packets in the buffer at that stage, or given a lower priority in the queue.

Maximum delay in buffered multistage interconnection networks

Abstract: The author studies maximum delay in buffered multistage interconnection networks. His model differs from most in its assumptions about the traffic entering the network. Instead of using a stochastic model for the entering traffic, it is assumed that the entering traffic is unknown but satisfies certain regularity constraints. In case these constraints would not otherwise be satisfied, it is possible to devise and analyze processing (and the associated delay) that can be performed so that the constraints are satisfied. The constraints considered are well suited for bounding parameters of interest. For example, bounds on maximum network delay for each user of the network are easily obtained. The methods presented can be applied to a wide variety of models for network operation and configuration. >

Support for high-priority traffic in VLSI communication switches

Abstract: The design of small n*n switches that can be used to construct communication networks that provide low-latency communication for high-priority traffic, which is required for both multistage interconnection networks used in multiprocessors and direct networks used in multicomputers. The focus is on the design of the internal buffers, specifically on the design of buffers that provide non-FIFO handling of messages. Alternative designs and configurations are evaluated in the context of a multistage interconnection network. Simulation shows that a slightly modified version of the recently introduced dynamically allocated multiqueue buffer can provide superior support for high-priority traffic. >

Analysis and design of nonequivalent multistage interconnection networks

Abstract: Nonequivalence of multistage interconnection networks is established by obtaining a reduced graph model and then partitioning it into several bipartite subgraphs. This is shown to transform nonequivalence to nonisomorphism, which can be easily determined by examining the intrinsic characteristics of undirected loops. A reverse process allows the design of nonequivalent networks. >

Time-Driven Parallel Simulation of Multistage Interconnection Networks

Abstract: MULTISTAGE INTERCONNECTION NETWORKS (MINS), AN IMPORTANT CLASS OF NET- WORKS ARISING IN HIGHLY PARALLEL COMPUTER SYSTEMS, ARE EXCELLEND CANDIDATES FOR PARALLEL TIME-DRIVEN SIMULATIONS ON SHARED MEMORY COMPUTER BECAUSE: 1) THEY ARE NATURALLY DISCRETE TIME SYSTEMS, 2) THEY (AND HENCE THEIR MODELS) ARE INHERENTLY PARALLEL AND MANY PACKETS ARE PROCESSED IN PARALLEL, AND 3) IT IS POSSIBLE TO EXPLOIT THEIR TOPOLOGICAL REGULARITY. IN THIS PAPER WE REPORT RESULTS ON THE PERFORMANCE OF SUCH SIMULATIONS ON AN 8 PROCESSOR SEQUENT SYMMETRY SYSTEM. WE SIMULATE BOTH INFINITE BUFFER AND FINITE BUFFER MINS. IN THE FORMER CASE WE CONSIDER SEVERAL MECHANISMS TO SYNCHRONIZE THE PROCESSORS AND FIND THAT A SIMPLE MULTIBARRIER MECHANISM THAT REQUIRES ALL PROCESSORS TO SYNCHRONIZE AFTER SIMULATING EACH MIN STAGE PROVIDES THE BEST PERFORMANCE. WE OBSERVE THAT TRAFFIC LOAD HAS LITTLE EFFECT ON SPEEDUP. ON THE OTHER HAND THE SIZE OF THE MIN BEING SIMULATED HAS A SIGNIFICANT EFFECT ON SPEEDUP. SPEEDUPS TYPICALLY RANGE FROM 4 WHEN THE MIN HAS 4 STAGES TO JUST OVER 7 WHEN THE MIN HAS 9 STAGES.

Properties of multistage interconnection networks

Abstract: Regular rectangular multistage interconnection networks that are complete and have the single path property are increasingly important in large parallel computing systems. The efficiency of such networks is critical to the overall system performance, and it depends on the structure, functional capabilities and routing control of the network. Much of the previous research has focused on specific networks. The objective of this dissertation is to study and characterize an important class of such networks. In particular, the relationships between network functionality and topology, switch size, control and modularity. The one-to-one correspondence between topology and functionality is shown, necessary and sufficient topological conditions for a network to realize all the permutations of another network are established, and optimal algorithms to decide if a network realizes all the permutations of another are developed. The single path property makes control via control tags potentially efficient. Two different control schemes are introduced where the control tags are the same as, or a function of, destination tags. The structure of these "easy-to-control" networks is shown to be recursive. Based on this recursiveness, the networks of several interesting network subclasses are shown to be functionally equivalent, namely, the subclass of doubly controllable networks, that is, easy-to-control from left to right and from right to left, the subclass of modular networks where all the stages are identical, and the subclass of r-ary networks, where the stages permute and transform $r$-ary digits. These single path networks do not realize all permutations. Multiple path Benes networks do but are a slow-to-control alternative. Accordingly, a new scheme for fast control of 3-stage Benes networks is introduced and studied, and several problems are shown to fit the new scheme, namely, biontic sorting, FFT, tree algorithms and matrix computations. Also, the random walk computation is parallelized and shown to fit this control scheme.

Fault-Tolerant Multistage Interconnection Networks for Multiprocessor Systems

Abstract: In this paper we present a class of multipath multistage interconnection networks (MINs) called Augmented Shuffle-Exchange Networks. These MINs can be designed to have the degree of switch fault tolerance desired. They feature links among switches belonging to the same stage, and the number of links between adjacent stages is the same as in unique path MINs. The paths available from a source to a destination have varying lengths. Rerouting in the presence of faults or blocking can be accomplished in these MINs dynamically, without resorting to backtracking. In addition to tolerating faults in individual switches, the proposed networks make it possible to tolerate faults in groups of switches, thus facilitating on-line repair. Reliability and performance studies show that the proposed MINs achieve a significant improvement over unique path MINs and compare favorably with other multiple path MINs.

Layout of large multistage interconnection networks technical field

Abstract: A technique for laying out large multistage interconnection networks. The invention provides for the division of a network into sub-networks which may be maintained on printed circuit boards and then provides for the addition of switching circuitry at the inputs or outputs of such boards such that pin locations on the boards may be swapped with each other to allow for a parallel interconnection of corresponding pins between the boards. Such parallel interconnection eliminates the existence of rat's nests in the wiring harness.

NxN interconnection networks formed of delta networks and method for the establishment of inlet-outlet permutations

Abstract: This invention discloses a new class of NxN multistage interconnection networks which is called class of Parallel Delta Networks (PDN). For such a class of networks the non-blocking conditions are given, i.e. those conditions which guarantee the capability of establishing any connection request between an inlet link and an outlet link, both supposed free whichever the state of the network may be. In particular, by means of the graph colouring technique it has been prov th the minimum number of Delta subnetworks necessary to provide the non-blocking property in a PDN is n ┌S/2┐-1, where S and n are the number of stages in a NxN Delta network and the number of inlet and outlet links of a single switching element, which Delta network consists of, respectively, and ┌x┐indicates the littlest whole number greater than x. For the establishment of the inlet-outlet connection request, a routing method has been defined. Such a method operates for switching elements of any size and in case of the set-up of a single connection request this method assures a complexity of the order of VN. In case of a whole set of inlet-outlet point-to-point connection requests (inlet-outlet permutation), this method has a polynomial complexity of the order N 3/2 . As the complexity relevant to the establishment of a single connection request is extremely low, this method is particularly suitable to an application in an environment in which the connection requests are asynchronous, i.e. a telecommunication environment. Therefore, this network can be used as connection network within an automatic exchange. It is also disclosed a variant of this method applicable in case the size of the single switching element is 2 q x2 q , where q is a whole number. Such a variant has a complexity of the order of N˙log 2 N and is suitable to a synchronous environment, in which the set of connection requests constitutes an inlet-outlet permutation.

Performance evaluation of nonrectangular multistage interconnection networks

Abstract: The performance is considered of unbuffered packet-switching nonrectangular multistage interconnection networks. Performance analysis is based on a simplified model for resolution of packet contention. An approximate closed-form analytical expression for the probability of packet acceptance is derived. Blocking characteristics of nonrectangular networks are analyzed and it is shown that for large nonrectangular networks, the probability of packet acceptance does not degrade with growth of network size. >

Performance analysis of multipath multistage interconnection networks

Abstract: This paper closely examines the performance analysis for unbuffered multipath multistage interconnection networks. A critical discussion of commonly used analysis is provided to identify a basic flaw in the model. A new analysis based on the grouping of alternate links is proposed as an alternative to rectify the error. The results based on the new analysis and extensive simulation are presented for three representative networks. The simulation study strongly supports the results of the new analysis.

Performance comparison of multistage cube-type interconnection networks

Abstract: The novel approach to the performance analysis of interconnection networks is developed to better understand their various properties and to form a basis for a more accurate evaluation of the real costs of a network implementation. The performance of the interconnection network is analyzed using a simplified model in a packet-switched environment in which queueing effects are neglected. The class of multistage interconnection networks known as the generalized cube and examined in detail, and its performance measures are compared. The influence of different control mechanisms on the network performance is discussed. >

Independent Connections: An Easy Characterization of Baseline-Equivalent Multistage Interconnection Networks.

Abstract: In this paper we study topological properties of multistage interconnection networks. We define the interconnection scheme between two stages as a pair of functions (f, g) which associate with a cell or node x, labelled as a binary string, his two sons f(x) and g(x). We consider a class of connections called independent connections. Using our graph characterization of networks topologically equivalent to the Baseline network, we show that all the Banyan networks built with independent connections are isomorphic. Finally, we show that if the interconnection scheme is defined by using permutations on the links induced by a permutation of the index digit (PIPID permutation) then the connection is independent. As these PIPID are associated with a very simple bit directed routing, they are used to define most of the networks introduced in the literature. Therefore all these networks are easily shown to be equivalent.

AN efficient method for the representation and transmission of message patterns

Abstract: A formalism is described for the compact representation of message patterns for multistage interconnection networks. In this formalism a descriptor called an (s,d)-mask is used to represent a message pattern, or rather, a set of messages. It is shown that when message patterns are represented in this way a number of their properties can be determined in polynomial time. This includes determining if a message pattern creates conflicts or congestion. In addition, it is shown that the minimum round partitioning problem, which in general is NP-complete, can be solved in polynomial time for any message pattern which can be represented by a single (s,d)-mask. The generalizes a known result to a more general class of message patterns and a more general class of networks. >

Partially Augmented Data Manipulator Networks: Minimal Designs and Fault Tolerance

Abstract: Augmented data manipulator networks are multistage interconnection networks which implement at each stage interconnection functions present in the single stage network known as PM2I network or barrel shifter. These multistage networks include the ADM (Augmented Data Manipulator) and IADM (Inverse Augmented Data Manipulator) networks, which have been extensively studied and proposed for use in multiprocessor systems. This paper derives new partially augmented networks based on the solution to the shortest path problem in the PM2I network. The new networks include: the HADM (Half Augmented Data Manipulator) and HIADM (Half Inverse Augmented Data Manipulator) networks which have half the number of stages of the ADM and IADM networks, the MADM (Minimum Augmented Data Manipulator) and the MIADM (Minimum Inverse Augmented Data Manipulator) networks which have the minimum link complexity required for one-to-one connections in a network of size N with log4 N stages of uniform switches, and the Extra Stage MADM and MIADM networks which are fault-tolerant versions of the MADM and MIADM networks that can tolerate at least three switch failures. The derivations of these networks are presented and their properties and advantages over other designs are analyzed.

SUPPORT FOR HIGH-PRIORITY TRAFFIC IN VLSI COMMUNICATION SWITCHES t

Abstract: Both multistage interconnection networks used in multiprocessors and direct networks used in multicomputers are composed of small nxn switches. The design of these switches is of critical importance for achieving high-bandwidth low-latency interprocessor communication. Interprocessor traffic generated by devices that must meet real-time requirements as well as certain other system activities, such as exception handling, may require particularly low communication latency. Special support for such high-priority traffic may thus be necessary in many multiprocessor and multicomputer systems. We discuss the design of nxn switches that can be used to construct communication networks which provide low latency communication for high-priority uaffic. We focus on the design of the internal buffers, specifically on buffers that provide non-FIFO handling of messages. We evaluate alternative designs and configurations in the context of a multistage interconnection network. Our simulations show that a slightly modified version of the recently introduced dynamically-allocated multi-queue buffer can provide superior support for high-priority traffic.