Showing papers on "Multistage interconnection networks published in 2003"
TL;DR: A survey of recent literature concerning switching schemes in the S/sup 3/ Clos network switch is provided and a new class of switching algorithms, called matching algorithms for Clos (MAC), is proposed to solve scheduling and route assignment simultaneously.
Abstract: Three-stage Clos network switches are an attractive solution for future broadband packet routers due to their modularity and scalability. Most three-stage Clos network switches assume either all modules are space switches without memory (bufferless), or employ shared memory modules in the first and third stages (buffered). The former is also referred to as the space-space-space (S/sup 3/) Clos network switch, while the latter is referred to as the memory-space-memory (MSM) Clos network switch. We provide a survey of recent literature concerning switching schemes in the S/sup 3/ Clos network switch. The switching problem in the S/sup 3/ Clos network switch can be divided into two major parts, namely port-to-port matching (scheduling) and route assignment between the first and third stages. Traditionally, researchers have proposed algorithms to solve these issues separately. Recently, a new class of switching algorithms, called matching algorithms for Clos (MAC), has been proposed to solve scheduling and route assignment simultaneously. We focus on the MAC schemes and show that the new class of algorithms can achieve high performance and maintain good scalability.
97 citations
TL;DR: How Clos' results have been generalized to systems that support connections with varying bandwidth requirements has extended the application of Clos networks well beyond their original technological context and has led to a number of interesting new results, especially in connection with systems thatSupport multicast communication.
Abstract: Clos networks are a class of multistage switching network topologies that provide alternate paths between inputs and outputs, making it possible to minimize or eliminate the blocking that can otherwise occur in such networks. In his seminal paper in the Bell System Technical Journal in 1953, Charles Clos showed how these networks could be configured to make them nonblocking and effectively launched the systematic study of switching system performance, a field that has developed a rich technical literature, and continues to be very active and of continuing practical importance. This article describes how Clos' results have been generalized to systems that support connections with varying bandwidth requirements. These generalizations have extended the application of Clos networks well beyond their original technological context and have led to a number of interesting new results, especially in connection with systems that support multicast communication.
89 citations
TL;DR: The article gives an overview of major theoretical issues associated with a switching network structure proposed by C. Clos (1953), showing the development of major research areas and a taxonomy of Clos switching networks.
Abstract: The article gives an overview of major theoretical issues associated with a switching network structure proposed by C. Clos (1953). The concepts of strict-sense and wide-sense nonblocking as well as repackable and rearrangeable networks are described, showing the development of major research areas. A taxonomy of Clos switching networks and some important results for the basic network structure are given and discussed. Other research issues are enumerated.
79 citations
TL;DR: The proposed bounds provide network designers an effective tool to estimate the minimum and maximum blocking probabilities of VSOB networks in which different routing strategies may be applied, and provide network developers a quantitative guidance to trade blocking probability for hardware cost.
Abstract: Banyan networks are attractive for constructing directional coupler (DC)-based optical switching networks for their small depth and self-routing capability. Crosstalk between optical signals passing through the same DC is an intrinsic drawback in DC-based optical networks. Vertical stacking of multiple copies of an optical banyan network is a novel scheme for building nonblocking (crosstalk-free) optical switching networks. The resulting network, namely vertically stacked optical banyan (VSOB) network, preserves all the properties of the banyan network, but increases the hardware cost significantly. Though much work has been done for determining the minimum number of stacked copies (planes) required for a nonblocking VSOB network, little is known on analyzing the blocking probabilities of VSOB networks that do not meet the nonblocking condition (i.e., with fewer stacked copies than required by the nonblocking condition). In this paper, we analyze the blocking probabilities of VSOB networks and develop their upper and lower bounds with respect to the number of planes in the networks. These bounds depict accurately the overall blocking behaviors of VSOB networks and agree with the conditions of strictly nonblocking and rearrangeably nonblocking VSOB networks respectively. Extensive simulation on a network simulator with both random routing and packing strategy has shown that the blocking probabilities of both strategies fall nicely within our bounds, and the blocking probability of packing strategy actually matches the lower bound. The proposed bounds are significant because they reveal the inherent relationships between blocking probability and network hardware cost in terms of the number of planes, and provide network developers a quantitative guidance to trade blocking probability for hardware cost. In particular, our bounds provide network designers an effective tool to estimate the minimum and maximum blocking probabilities of VSOB networks in which different routing strategies may be applied. An interesting conclusion drawn from our work that has practical applications is that the hardware cost of a VSOB network can be reduced dramatically if a predictable and almost negligible nonzero blocking probability is allowed.
57 citations
01 Jan 2003
TL;DR: A new tool for stochastic simulation of multistage interconnection networks that are arranged in multiple layers as well as simple crossbars can be simulated.
Abstract: Multistage interconnection networks are frequently proposed as connections in multiprocessor systems or network switches In this paper, a new tool for stochastic simulation of such networks is presented Simple crossbars can be simulated as well as multistage interconnection networks that are arranged in multiple layers
25 citations
TL;DR: It is proved that the set of admissible permutations for a MIN can be partitioned in Latin Squares, and a method to realize the complete exchange with time complexity O(N), that is optimal, can be derived.
23 citations
TL;DR: This article focuses on the three-stage Clos network and its recursive extensions and provides some fresh viewpoints to either clarify or simplify some issues.
Abstract: The author gave a survey on multicast nonblocking multistage interconnection networks in his 1998 book. Here he focuses on the three-stage Clos network and its recursive extensions. Not only does this article bring the literature up to date, but it also provides some fresh viewpoints to either clarify or simplify some issues.
21 citations
TL;DR: It is shown that performance degradation due to fault tolerance is graceful while performance degradation without fault recovery is unacceptable, and new performance models are developed and used to evaluate the compound effect of fault tolerant operation on the overall throughput and delay.
Abstract: Performance and reliability are two of the most crucial issues in today's high-performance instrumentation and measurement systems. High speed and compact density multistage interconnection networks (MINs) are widely-used subsystems in different applications. New performance models are proposed to evaluate a novel fault tolerant MIN arrangement, thereby assuring performance and reliability with high confidence level. A concurrent fault detection and recovery scheme for MINs is considered by rerouting over redundant interconnection links under stringent real-time constraints for digital instrumentation such as sensor networks. A switch architecture for concurrent testing and diagnosis is proposed. New performance models are developed and used to evaluate the compound effect of fault tolerant operation (inclusive of testing, diagnosis, and recovery) on the overall throughput and delay. Results are shown for single transient and permanent stuck-at faults on links and storage units in the switching elements. It is shown that performance degradation due to fault tolerance is graceful while performance degradation without fault recovery is unacceptable.
18 citations
TL;DR: The structure of the MIN is derived first by transforming the de Bruijn interconnection-based Viterbi algorithm trellis into the equivalenttrellis with a perfect shuffle interconnection, and then applying a new decomposition of the perfect shuffle operator.
Abstract: We propose new multistage interconnection networks (MIN) for scalable parallel Viterbi decoder architectures. The architecture consists of the desired number of processing elements (PE) connected by the suggested MINs, thus allowing a tradeoff between complexity and speed. The structure of the MIN is derived first by transforming the de Bruijn interconnection-based Viterbi algorithm trellis into the equivalent trellis with a perfect shuffle interconnection, and then applying a new decomposition of the perfect shuffle operator. This results in an efficient modular system and data flow is formed by the shuffling in a local PE memory and data exchange through a fixed interconnection between PEs. We suggest several solutions for 1/n and k/n rate codes, where k denotes the number of input bits shifting into k shift registers of the encoder and, at each cycle, the encoder produces n output bits as linear combinations of certain bits in the shift registers.
17 citations
20 Oct 2003
TL;DR: The permutation capacity of MINs is reexamine, a simpler proof for semipermutation decomposability is presented, and a parallel decomposition algorithm of logarithmic time is proposed that is useful for optimally routing crosstalk-free paths in optical Benes networks in high-speed.
Abstract: Multistage interconnection networks (MINs) can be used to construct electro-optic switches. To implement crosstalk-free switching in such a switch, two I/O connecting paths cannot share a common switching element (SE). Thus, a permutation must be decomposed into partial permutations, each being routed through the switch without crosstalk. It was shown that any permutation can be decomposed into two semipermutations, and each is a maximum partial permutation realizable in one pass in an optical Benes network. However, the time complexity of existing decomposition algorithms for realizing connection requests is proportional to permutation size. In this paper, we reexamine the permutation capacity of MINs, present a simpler proof for semipermutation decomposability, and propose a parallel decomposition algorithm of logarithmic time. This algorithm is shown useful for optimally routing crosstalk-free paths in optical Benes networks in high-speed.
16 citations
01 Dec 2003
TL;DR: This model calculates the blocking probabilities stage by stage recursively, and it depicts accurately the blocking behaviors of VSOB networks under random routing, and reveals the inherent relationships between blocking probability and network hardware cost in terms of the number of planes.
Abstract: Vertical stacking of optical banyan networks is an attractive scheme for building nonblocking (crosstalk-free) optical switching networks. The resulting networks, namely vertically stacked optical banyan (VSOB) networks, preserve all the good properties of banyan networks, but increase the hardware cost significantly. In this paper, we study the blocking probabilities of VSOB networks under random routing strategy, and develop a model to compute the blocking probabilities with respect to the number of planes in the networks. Our model calculates the blocking probabilities stage by stage recursively, and it depicts accurately the blocking behaviors of VSOB networks under random routing. The proposed model is significant because it reveals the inherent relationships between blocking probability and network hardware cost in terms of the number of planes, and provides network developers a quantitative guidance to find a desirable tradeoff between blocking probability and hardware cost. An important conclusion drawn from our work that has practical applications is that the hardware cost of a VSOB network can be reduced dramatically if a predictable and almost negligible non-zero blocking probability is allowed.
22 Apr 2003
TL;DR: A performance evaluation and comparison methodology is applied on a new interconnection network called MCRB network and on Omega network using what it thinks of as the most important parameters to be considered when solving such a problem.
Abstract: Interconnection network performance is a key factor when constructing parallel computers. The choice of an interconnection network used in a parallel computer depends on a large number of performance factors which are very often application dependent. We give the outline of a performance evaluation and comparison methodology using what we think of as the most important parameters to be considered when solving such a problem. This methodology is applied on a new interconnection network called MCRB network and on Omega network.
DOI•
01 Jan 2003TL;DR: A novel adaptive resequencer that adjusts the time cells spend waiting in the resequencing buffer, based on the recent history of the interconnection network delay is proposed, which is suitable for systems with link speeds of up to 40 Gb/s.
Abstract: Multistage interconnection networks with internal cell buffering and dynamic routing are among the most cost-effective architectures for multiterabit internet routers. One of the key design issues for such systems is maintaining cell ordering, since cells are subject to varying delays as they pass through the interconnection network. The most flexible and scalable approach to cell resequencing uses timestamps and a time-ordered resequencing buffer at each router output port. Conventional, fixed-threshold resequencers can perform poorly in the presence of extreme traffic conditions. This paper explores alternative resequencer designs that are more tolerant of such traffic. These alternatives include a novel adaptive resequencer that adjusts the time cells spend waiting in the resequencing buffer, based on the recent history of the interconnection network delay. The design is straightforward to implement and requires only constant time per cell, making it suitable for systems with link speeds of up to 40 Gb/s. We show that the combination of adaptive resequencing and appropriately designed interconnection networks can limit resequencing errors to negligible levels without requiring large resequencing latencies. This work is supported by the Defense Advanced Research Projects Agency (contract N660001-01-1-8930).
TL;DR: A tag-based routing algorithm for the backward network is proposed, so as to reduce the computation of the shuffle-exchange operation.
Abstract: We enhance the general shuffle-exchange network (GSEN) with bidirectional links. For bidirectional links, the bidirectional GSEN can be divided into two dependent networks, forward network and backward network. Based on the idea of inversely using the forward tag, we propose a tag-based routing algorithm for the backward network, so as to reduce the computation of the shuffle-exchange operation.
24 Jun 2003
TL;DR: The paper presents a flow merging scheme that is needed to bring the cost of backpressure down to O(N) per switching element, and proves freedom from deadlock for a wide class of multipath cell distribution algorithms.
Abstract: Multistage buffered switching fabrics are the most efficient method for scaling packet switches to very large numbers of ports. The Benes network is the lowest-cost switching fabric known to yield operation which is free of internal blocking. Backpressure inside a switching fabric can limit the use of expensive off-chip buffer memory to just virtual-output queues (VOQ) in front of the input stage. The paper extends the known backpressure architectures to the Benes network. To achieve this, we had to combine per-flow backpressure, multipath routing (inverse multiplexing), and cell resequencing successfully. We present a flow merging scheme that is needed to bring the cost of backpressure down to O(N) per switching element. We prove freedom from deadlock for a wide class of multipath cell distribution algorithms. Using a cell-time-accurate simulator, we verify that operation is free of internal blocking, we evaluate various cell distribution and resequencing methods, we compare performance to that of ideal output queueing and the iSLIP crossbar scheduling algorithm, and we show that the delay of well-behaved flows remains unaffected by the presence of congested traffic to oversubscribed output ports.
TL;DR: A three-stage switching system that uses optical WDM grouped links and dynamic bandwidth sharing to expand the throughput of the switching system up to 5 Tb/s and confirms the scalability and cost-effectiveness of this switch.
Abstract: A three-stage Clos switch architecture is attractive because of its scalability. From an implementation point of view, it allows us to relax the cooling limitation, but there is a problem interconnecting different stages. This article presents a three-stage switching system that uses optical WDM grouped links and dynamic bandwidth sharing. We call it a WDM grouped-link switch. The introduction of WDM makes the number of cables used in the system proportional to the switch size. Dynamic bandwidth sharing among WDM grouped links prevents the statistical multiplexing gain offered by WDM from falling even if the switching system becomes large. The WDM grouped-link switch uses cell-by-cell wavelength routing. A performance evaluation confirms the scalability and cost-effectiveness of this switch. An implementation of the WDM grouped link and a compact planar lightwave circuit platform is described. This architecture allows us to expand the throughput of the switching system up to 5 Tb/s.
20 Oct 2003
TL;DR: An optical multistage interconnection network to realize an all-to-all personalized exchange that only requires one pass to send a message from each node to a different node (to realize a permutation) in the network is proposed.
Abstract: All-to-all personalized exchange is one of the most dense collective communication patterns and it occurs in many parallel and distributed computing applications. Advances in electro-optic switches have made optical communication a good networking choice that can satisfy the high channel bandwidth and low communication latency of high performance computing/communication applications. Let n be the number of nodes in a network. Previously proposed optical multistage networks require at least two passes to send a message from each node to a different node (to realize a permutation) in the network. That is, 2n passes are needed to realize an all-to-all personalized exchange. We propose an optical multistage interconnection network to realize an all-to-all personalized exchange that only requires one pass to send a message from each node to a different node (to realize a permutation). Hence, the new optical multistage interconnection network only requires n-1 passes for an all-to-all personalized exchange instead of 2n passes.
TL;DR: The design and successful operation of an optoelectronic Hopfield network demonstrator system, based around a free-space diffractive optical interconnect, was designed to perform a range of optimization tasks, in particular those associated with the scheduling of packets through different switching topologies.
Abstract: We describe the design and successful operation of an optoelectronic Hopfield network demonstrator system. The Hopfield network, one of the simpler space-invariant interneuronal connection networks, was chosen due to its observed efficiency in solving optimization tasks. The demonstrator system, based around a free-space diffractive optical interconnect, was designed to perform a range of optimization tasks, in particular those associated with the scheduling of packets through different switching topologies. Experimental optimization of the neural network throughput, for both a crossbar and Banyan switch topology, allows the neural network parameters (e.g., neuron bias, neuron weighting) to be tuned to ensure optimal operation of the network for a particular switch topology. In addition, the demonstrator allows an investigation of the critical parameters governing the interoperation of the different modules. In this paper, we describe the effect of two of these parameters, namely, the operating temperature of the optoelectronic devices and the accuracy of the interconnection fabrication technology. The weighted interconnections in this optoelectronic system are provided by a diffractive optical element/lens combination whilst the neurons are implemented electronically. The transition between the electronic and optical domains is handled by an 8/spl times/8 VCSEL array for the electronic-optic interface, and an 8/spl times/8 Si photodetector array for the optic-electronic interface. The VCSEL array consists of oxide-confined near-infrared GaAs devices capable of 250-MHz modulation at a wavelength of 960 nm. The diffractive optical interconnect is designed using simulated annealing optimization and fabricated using very large scale integration photolithography. Using these techniques, it is possible to create interconnects with a total efficiency of /spl sim/70% and a nonuniformity of <1%.
20 Oct 2003
TL;DR: In this paper, the authors determine the sufficient condition for rearrangeable nonblocking optical multistage interconnection networks to tolerate a stricter crosstalk constraint without increasing their hardware complexity significantly.
Abstract: Optical networks suffer from the intrinsic crosstalk problem that should be overcome to make optical networks work properly. Vertical stacking of an optical banyan network is a novel scheme for constructing nonblocking optical multistage interconnection networks (MINs), and rearrangeable nonblocking optical MINs are feasible since they have lower complexity than their strictly nonblocking counterparts. We determine the sufficient condition for these MINs to be rearrangeable nonblocking under various crosstalk constraints. We show how the crosstalk constraint affects the design of rearrangeable nonblocking MINs and demonstrate that these networks can tolerate a stricter crosstalk constraint without increasing their hardware complexity significantly. The results will be useful in designing optical MINs with reasonable hardware cost and crosstalk level.
20 Oct 2003
TL;DR: Results show that TC-chain node Banyan network offer an improved throughput-delay ratio performance under both traffic models.
Abstract: Internally buffered multistage interconnection network (MIN) architectures have been widely used in parallel computer systems and large switching fabrics. Migration from electrical domain to optical domain has raised the necessity of developing node architectures with optical buffers. Cascaded optical delay line(COD) emulates output buffering in a 2/spl times/2 switching element. Two versions of COD are track changer (TC) and twin track changer (TTC). These approaches can be used as a buffered switching element in a Banyan like MIN. We investigate and compare these approaches by using simulation methods. Different performance metrics, such as throughput-delay ratio, packet loss rate have been used under uniform and nonuniform traffic models. Results show that TC-chain node Banyan network offer an improved throughput-delay ratio performance under both traffic models.
09 Jul 2003
TL;DR: An analytical model is developed here that provides not only the nonblocking conditions of three-stage multicast networks, but also the evaluation of the blocking probability when such conditions are not satisfied.
Abstract: This paper considers three-stage switching networks able to support multicast traffic, i.e. connections in which one inlet is connected to more than one output at the same time. The nonblocking conditions for this network are studied under the assumption of absence of any optimized routing of the connections inside the structure (the so-called strict-sense nonblocking networks). An analytical model is developed here that provides not only the nonblocking conditions of three-stage multicast networks, but also the evaluation of the blocking probability when such conditions are not satisfied. Unlike previous well-known approaches, our model takes into account the correlation between occupancy events in links belonging to different interstage patterns. The results being found also provide a more stringent condition of network nonblocking for multicast traffic which disproves some of the claimed results recently published in the technical literature.
26 Mar 2003
TL;DR: This work introduces a new approach to implement a transparent all-optical, non-blocking cross connect switch for routing optical network traffic, based on the combination of MEMS, diffractive optical elements, and optical fibers.
Abstract: Fiber-optic communication has provided the information technology revolution with the high data rate networks it needed. A severe limitation of current fiber networks is caused by the use of electronics in switching and routing. An all-optical fiber network, where there is no need for signal conversion between optics and electronic, is the answer to such a demand. We introduce a new approach to implement a transparent all-optical, non-blocking cross connect switch for routing optical network traffic. This approach is based on the combination of MEMS, diffractive optical elements, and optical fibers. The proposed cross-connect is programmable to configure the network as needed. We develop MINs (multistage interconnection networks), using MEMS based switches as the backbone, to support multicast while reducing crosstalk and control complexity. We develop reordering algorithms and design a slot permuter to adapt to all changes for multicast support. The slot permuter permutes the slots in a frame over time. Finally, we verify the performance and effectiveness of our algorithms and the slot permuter through theoretical analysis and extensive simulation.
TL;DR: The sufficient and necessary conditions under which a three-stage Clos network is rearrangeable for multicast connections are given and it is assumed that only switches of the middle stage have the fan-out property.
Abstract: The sufficient and necessary conditions under which a three-stage Clos network is rearrangeable for multicast connections are given. It is assumed that only switches of the middle stage have the fan-out property. Such an assumption is valid for some practical switching systems, e.g., high-speed crossconnects.
TL;DR: The tabulation methodology follows the same diagnostic procedure for the various infrastructures and is independent of the size of the DOMINs, and a computer program can simulate the procedure and the results support the optimal test.
09 Apr 2003
TL;DR: The single-buffer performance model is developed and evaluated, and some results are given.
Abstract: In this paper, we propose the C1-networks, including the complete C1-networks and the incomplete C1-networks, which evolved from the B-networks. The main difference between the complete C1-network and the B-network is their connecting pattern between the stages. The available MINs to date are almost all restricted by the port number in the power of 2. The C1-network is not under the control of this restriction, hence, good flexibility is obtained. In addition, the single-buffer performance model is developed and evaluated, and some results are given.
TL;DR: The concept of disjoint faults is extended to reduce the number of tests to the time efficiency of Θ(N(superscript 5/6) for N×N DOMINs, and an algorithm is proposed herein to find the maximum number of disJoint faults.
Abstract: Dilated Optical Multistage Interconnection Networks (DOMINs) based on 2×2 directional coupler photonic switches play an important role in all-optical high-performance networks, especially for the emerging IP over DWDM architectures. The problem of crosstalk within photonic switches is underestimated due to the aging of the switching element, control voltage, temperature and polarization, and thus causes undesirable coupling of the signal from one path to the other. Previous works [18] designed an efficient diagnosing disjoint faults algorithm in small sized networks, which reduced the number of tests required by overlapping the tests with computations to one half in photonic switching networks. Furthermore, this paper generically derives algorithms and mathematical modules to find the optimal degree of parallelism of faults diagnosis for N×N dilated blocking networks, as the size of network is larger. Taking advantage of the properties of disjoint faults, diagnosis can be accelerated significantly because the optimal degree of parallel fault diagnosis may grow exponentially. To reduce the diagnosis time, an algorithm is proposed herein to find the maximum number of disjoint faults. Rather than requiring up to 4MN tests as a native approach, a two-phase diagnosis algorithm is proposed to reduce the testing requirement to 4N tests. This study extends the concept of disjoint faults to reduce the number of tests to the time efficiency of Θ(N(superscript 5/6)) for N×N DOMINs.
30 Apr 2003
TL;DR: This paper proposes a large NxN MEMS-based optical switch (OXC) architecture design by using small-port switch modules that can increase the port number of MEMs-based 2D OXC significantly and improve its performance notably.
Abstract: In this paper, we proposed a large NxN MEMS-based optical switch (OXC) architecture design by using small-port switch modules. Two types of integrated multistage switch: Banyan switch and Clos switch with nonblocking in strict sense property are designed. Our proposed architecture can increase the port number of MEMS-based 2D OXC significantly and improve its performance notably.
TL;DR: Two types of dilated re-arrangeable networks extended from dilated blocking networks are presented: a class of two cascaded dilatedblocking networks, such as dilated_blocking_network- dilated- blocking_network architectures, and the other type can be extended from the dilated blocked networks, i.e. horizontal cascading (HC) or vertical stacking (VS).
14 Oct 2003
TL;DR: Simulation results show that the critical fault sets with respect to the property of dynamic-full-access with fixed control values (DFA-FC), are exactly those critical with respectto the property with changeable controlvalues (D FA-CC).
Abstract: In this paper, we present an experimental and theoretical analysis of the dynamic-full-access property for two classes of multistage interconnection networks (MIN's). For the first class of MIN's, simulation results show that the critical fault sets with respect to the property of dynamic-full-access with fixed control values (DFA-FC), are exactly those critical with respect to the property of dynamic-full-access with changeable control values (DFA-CC). For the same class, we present a formal proof of this observation for a large class of critical fault sets. For the second class of MIN's, namely the butterfly networks, the simulation results show that this type of MIN's has the same critical fault sets with respect to either one of the two preceding properties.