Showing papers on "Multistage interconnection networks published in 2010"

Multistage Interconnection Networks: A Transition from Electronic to Optical

Abstract: Optical communication are necessary for achieving reliable, fast and flexible communication . Advances in electro-optic technologies have made optical communication a reliable networking choice to meet the increasing demands for high bandwidth and low communication latency of high-performance computing/communication applications. So optical networks gives high performance as well as low latency. Alth ough optical MINs hold great promise and have advantages over their electronic networks, they also hold their own challenges. This paper compares electronic and Optical MINs. The design issues and solution approaches available for optical MINs are also explained and analyzed.

Performance study of multilayered multistage interconnection networks under hotspot traffic conditions

Abstract: The performance of Multistage Interconnection Networks (MINs) under hotspot traffic, where some percentage of the traffic is targeted at single nodes, which are also called hot spots, is of crucial interest. The prioritizing of packets has already been proposed at previous works as alleviation to the tree saturation problem, leading to a scheme that natively supports 2-class priority traffic. In order to prevent hotspot traffic from degrading uniform traffic we expand previous studies by introducing multilayer Switching Elements (SEs) at last stages in an attempt to balance between MIN performance and cost. In this paper the performance evaluation of dual-priority, double-buffered, multilayer MINs under single hotspot setups is presented and analyzed using simulation experiments. The findings of this paper can be used by MIN designers to optimally configure their networks.

TROUTE: a reconfigurability-aware FPGA router

Abstract: Since FPGAs are inherently reconfigurable, making FPGA designs generic does not reduce chip cost, as is the case for ASICs. However, designing and mapping lots of specialized FPGA designs introduces an extra EDA cost. We describe a two staged fully automatic FPGA tool flow that efficiently maps a generic HDL design to multiple specialized FPGA configurations. The mapping is fast enough to be executed on-line in dynamically reconfigurable systems. In this paper we focus on troute, the routing algorithm used in our tool flow. We used troute to implement reconfigurable Multistage Interconnection Networks and show huge improvements in area, speed and mapping time compared to conventional non-reconfigurable implementations.

An Approximate Analytical Performance Model for Multistage Interconnection Networks with Backpressure Blocking Mechanism

Abstract: Multistage Interconnection Networks (MINs) are used to interconnect different processing modules in various parallel systems or on high bandwidth networks. In this paper an integrated performance methodology is presented. A new approximate performance model for self-routing MINs consisting of symmetrical switches which are subject to a backpressure blocking mechanism is analyzed. Based on this, the steady-state distribution of the queue utilization is estimated and then all important performance metrics are calculated. Moreover, a general evaluation factor which helps in choosing a better performance MIN in comparison with other similar MIN architecture specifications is defined. The model was exemplified for the case of symmetrical single- and double-buffered MINs. It provides accurate results and converges very quickly. The obtained results were validated by extensive simulations and were compared to existing related work in the literature.

Reliability and path length analysis of irregular fault tolerant multistage interconnection network

Abstract: In this paper reliability and path length analysis of irregular Multistage Interconnection Networks have been presented. We have examined FT(Four Tree)[8],MFT(Modified Four Tree)[2],NFT(New Four Tree)[4],IFT(improved Four Tree)[5],IASN(Irregular Augmented Shuffle)[14] and IIASN(Improved Irregular Augmented Shuffle)[3] networks in which the number of switches in each stage are different in numbers and also have express links[11]. Using upper and lower bounds[7][13][15] for larger networks, the reliability[9] in terms of mean time to failure of all these networks are evaluated and compared with each other. Each source is connected to destination with one or multiple paths with varying path lengths in a network. The path length analysis of all these networks is also analyzed in this paper. A path length[8] algorithm for IIASN network is also propose

Fast zerox algorithm for routing in optical multistage interconnection networks

Abstract: Based on the ZeroX algorithm, a fast and efficient crosstalk-free time- domain algorithm called the Fast ZeroX or shortly FastZ_X algorithm is proposed for solving optical crosstalk problem in optical Omega multistage interconnection networks. A new pre-routing technique called the inverse Conflict Matrix (iCM) is also introduced to map all possible conflicts identified between each node in the network as another representation of the standard conflict matrix commonly used in previous Zero-based algorithms. It is shown that using the new iCM, the original ZeroX algorithm is simplified, thus improved the algorithm by reducing the time to complete routing process. Through simulation modeling, the new approach yields the best performance in terms of minimal routing time in comparison to the original ZeroX algorithm as well as previous algorithms tested for comparison in this paper.

The Development of Crosstalk-Free Scheduling Algorithms for Routing in Optical Multistage Interconnection Networks

Abstract: Advances in electro-optic technologies have made optical communication a promising networking alternative to meet the ever increasing demands of high-performance computing communication applications for high channel bandwidth, low communication latency and parallel processing as well. Optical Multistage Interconnection Network (OMIN) is popular in switching and communication applications and has been studied extensively as an important interconnecting scheme for communication and parallel computing systems. The OMIN is frequently proposed as connections in multiprocessor systems or in high bandwidth network switches. A major problem in OMIN is optical crosstalk. It is caused by coupling two signals within a Switching Element (SE). Crosstalk problem in a switch is the most prominent factor, which reduces the signal-to-noise ratio and restricts the size of a network. Various methods to decrease the undesirable effect of crosstalk have been proposed, that apply the concept of dilation in either the space, time or wavelength domains. With the space domain approach, additional SE(s) and links are used to certify that at most only one input and one output of every SE will be active at any given time. With the time domain approach, two connections will be activated at different time slots if they share the same SE in any stage of the network. The last approach, the wavelength domain, different wavelengths are used for routing active connections by ensuring two wavelengths entering an SE to be far apart by routing or using wavelength converters. Whenever the limitation of the network size is reached, the time domain method may be used as a feasible way to trade the maximal bandwidth available to each particular input and output pair for enhanced connectivity. Again, it is useful when future technology let the transmission rate to expand faster than the network size or when the cost of expanding the bandwidth of each connection becomes as “cheap” as the cost of building a network of twice its original size. The chapter covers the development of crosstalk-free scheduling algorithms for routing in an OMIN. The interest is on how to efficiently schedule messages using the time domain approach in order to avoid crosstalk. In the time domain approach, messages to be sent to the network are distributed into several groups for routing at different time slots. There are 29

Unified algebraic theory of sorting, routing, multicasting, and concentration networks

Abstract: Multistage interconnection networks (MINs) are commonly deployed in sorting, switching, and other applications. Arithmetic over MINs for various applications is hereby unified in algebra. The key is to structure the signal alphabet as a distributive lattice instead of an ordered set. The theoretic unification enhances the mathematical understanding of properties of MINs and, in particular, demystifies various 0-1 principles. Conventional applications of MINs are all for point-to-point transmissions, while the unified theory applies to multicasting as well. The Multicast Concentrator Theorem is generalized into the Boolean Concentrator Theorem, which is useful in recursive construction of multicast switches with the feature of priority treatment. Meanwhile, the concomitant theory of cut-through coding is introduced for delay-free signal propagation through a MIN.

A Scalable and Early Congestion Management Mechanism for MINs

Abstract: Several packet marking-based mechanisms have been proposed to manage congestion in multistage interconnection networks. One of them, the MVCM mechanism obtains very good results for different network configurations and traffic loads. However, as MVCM applies full virtual output queuing at origin, its memory requirements may jeopardize its scalability. Additionally, the applied packet marking technique introduces certain delay to detect congestion. In this paper, we propose and evaluate the Scalable Early Congestion Management mechanism which eliminates the drawbacks exhibited by MVCM. The new mechanism replaces the full virtual output queuing at origin by either a partial virtual output queuing or a shared buffer, in order to reduce its memory requirements, thus making the mechanism scalable. Also, it applies an improved packet marking technique based on marking packets at output buffers regardless of their marking at input buffers, which simplifies the marking technique, allowing also a sooner detection of the root of a congestion tree.

FPGA-accelerated Attractor Computation of Scale Free Gene Regulatory Networks

Abstract: Due to the large amount of experimental data provided by DNA microarrays, different kinds of computational methods have been proposed to study gene interactions. These methods are computationally very intensive. More specifically, this work focuses on an efficient approach to compute the attractor cycles in gene regulatory networks, which are modeled by Boolean graphs. This work proposes to explore the inherent parallelism of this approach by using a FPGA based implementation. In addition, we also propose a runtime framework to dynamically insert/delete edges at low cost by using a multistage interconnection network (MIN). We also show that MIN could be efficiently mapped on FPGAs by taking advantages of embedded memory modules. The MIN implementation is close to theoretical complexity O(n lg n). Moreover, we propose a heterogeneous node set, where few nodes are strongly connected and most nodes are poorly connected, which allow us to handle efficiently scale free topologies. Furthermore, our approach is synthesized once onto a FPGA and several simulations are performed, without the need of re-synthesis. Experimental results have shown acceleration gains up to three orders of magnitude compared to sequential approaches.

Effect of Crosstalk on Permutation in Optical Multistage Interconnection Networks

Abstract: Optical MINs hold great promise and have advantages over their electronic networks.they also hold their own challenges. More research has been done on Electronic Multistage Interconnection Networks, (EMINs) but these days optical communication is a good networking choice to meet the increasing demands of high-performance computing communication applications for high bandwidth applications. The electronic Multistage Interconnection Networks (EMINs) and the Optical Multistage Interconnection Networks (OMINs) have many similarities, but there are some fundamental differences between them such as the optical-loss during switching and the crosstalk problem in the optical switches. To reduce the negative effect of crosstalk, various approaches which apply the concept of dilation in either the space or time domain have been proposed. With the space domain approach, extra SEs are used to ensure that at most one input and one output of every SE will be used at any given time. For an Optical network without crosstalk, it is needed to divide the messages into several groups, and then deliver the messages using one time slot (pass) for each group, which is called the time division multiplexing. This Paper discusses the permutation passability behavior of optical MINs. The bandwidth of optical MINs with or without crosstalk has also been explained. The results thus obtained shows that the performance of the networks improves by allowing crosstalk to some extent.

Efficient topologies for large-scale cluster networks

Abstract: Increasing integrated-circuit pin bandwidth has motivated a corresponding increase in the degree or radix of interconnection networks and their routers. This paper describes the flattened butterfly, a cost-efficient topology for high-radix networks. On benign (load-balanced) traffic, the flattened butterfly approaches the cost/performance of a butterfly network and has roughly half the cost of a comparable performance Clos network. The advantage over the Clos is achieved by eliminating redundant hops when they are not needed for load balance. On adversarial traffic, the flattened butterfly matches the cost/performance of a folded-Clos network and provides an order of magnitude better performance than a conventional butterfly. In this case, global adaptive routing is used to switch the flattened butterfly from minimal to non-minimal routing — using redundant hops only when they are needed. Different routing algorithms are evaluated on the flattened butterfly and compared against alternative topologies. We also provide a detailed cost model for an interconnection network and compare the cost of the flattened butterfly to alternative topologies to show the cost advantages of the flattened butterfly.

Rearrangeable nonblocking optical interconnection network fabrics with crosstalk constraints

Abstract: In this paper, we studied the necessary and sufficient conditions for Banyan-type networks, which are rearrangeable nonblocking (RNB) by considering all possible degrees of crosstalk constraints. To the best of our knowledge, this paper is the first one to propose a comprehensive solution that takes into account of all the possible crosstalk constraints for optical interconnection network fabrics. Therefore, the necessary and sufficient RNB conditions for optical interconnection networks under various crosstalk constraints are defined completely. Moreover, we found the conditions are independent from the degree of crosstalk constraint. It means the number of needed planes will not increase due to a stricter constraint by allowing a lower degree of crosstalk unless it goes down to zero crosstalk. It also signifies that a much stricter degree of crosstalk constraint could be imposed without changing the hardware fabrics. These conditions provide the useful tips for a cost-effective design of such optical interconnection networks.

Analyzing Nonblocking Switching Networks using Linear Programming (Duality)

Abstract: The main task in analyzing a switching network design (including circuit-, multirate-, and photonic-switching) is to determine the minimum number of some switching components so that the design is non-blocking in some sense (e.g., strict- or wide-sense). We show that, in many cases, this task can be accomplished with a simple two-step strategy: (1) formulate a linear program whose optimum value is a bound for the minimum number we are seeking, and (2) specify a solution to the dual program, whose objective value by weak duality immediately yields a sufficient condition for the design to be non-blocking. We illustrate this technique through a variety of examples, ranging from circuit to multirate to photonic switching, from unicast to $f$- cast and multicast, and from strict- to wide-sense non-blocking. The switching architectures in the examples are of Clos-type and Banyan- type, which are the two most popular architectural choices for designing non- blocking switching networks. To prove the result in the multirate Clos network case, we formulate a new problem called {\sc dynamic weighted edge coloring} which generalizes the {\sc dynamic bin packing} problem. We then design an algorithm with competitive ratio $5.6355$ for the problem. The algorithm is analyzed using the linear programming technique. We also show that no algorithm can have competitive ratio better than $4-O(\log n/n)$ for this problem. New lower- and upper-bounds for multirate wide-sense non-blocking Clos networks follow, improving upon a couple of $10$-year-old bounds on the same problem.

Non-blocking conditions for EGS networks

Abstract: A class of multistage interconnection networks, known as extended generalized shuffle (EGS) network, is here considered; it is built with arrays of elementary switching elements, interconnected by shuffle patterns, and external splitters and combiners. New results are given here that reduce the splitter fanout required to make the network strictly non-blocking.

An Asynchronous Routing Algorithm for Clos Networks

Abstract: Clos networks provide the theoretically optimal solution to build high-radix switches. This paper proposes a novel asynchronous routing algorithm for general asynchronous three-stage Clos networks. As the major sub-algorithm controlling the first two stages, the asynchronous dispatching algorithm outperforms the synchronous concurrent round-robin dispatching algorithm in behaviour level simulations. In a 32-port Clos network utilizing the asynchronous routing algorithm, paths are reserved in 6.2 ns and released in 3.9 ns.

On a Fast Interconnections

Abstract: Summary In this paper, we have discussed tool called Fast Interconnection, which have been designed for developing fault-tolerant multistage interconnection networks. The designed tool is one of its own kind and will help the user in developing 2 and 3-disjoint path networks.

Rearrangeability in multicast clos networks is np-complete

Abstract: Three-stage Clos networks are commutation networks with circuit switching. So far, graph theory has been very useful tool for solving issues related to these networks with unicast connections. This is so because if Clos network is represented as a bipartite graph then connecting paths are easy transformed into edge coloring. It is also natural to use on-line edge coloring algorithms. However, the things get more complicated in case of multicast connections. There are four models of multicast 3-stage Clos networks: model-1 where only the first stage switches do not have fan-out capability, model-2 where only the second stage switches do not have fan-out capability, model-3 where only the third stage switches do not have fan-out capability and model-0 where no switches lack fan-out capability. In the paper we show some new results on model-0 and model-1 multicast Clos networks. In particular, we focus on rearrangeable multicast networks and prove that the problem of their rearranging is NP-complete.

Twister Networks and Their Applications to Load-Balanced Switches

Abstract: Inspired by the recent development of optical queueing theory, in this paper we study a class of multistage interconnection networks (MINs), called {\em twister networks}. Unlike the usual recursive constructions of MINs (either by two-stage expansion or by three-stage expansion), twister networks are constructed {\em directly} by a concatenation of bipartite networks. Moreover, the biadjacency matrices of these bipartite networks are sums of subsets of the powers of the circular shift matrix. Though MINs have been studied extensively in the literature, we show there are several {\em distinct} properties for twister networks, including routability and conditionally nonblocking properties. In particular, we show that a twister network satisfying (A1) in the paper is routable, and packets can be self-routed through the twister network by using the $\cal C$-transform developed in optical queueing theory. Moreover, we define an $N$-modulo distance and use it to show that a twister network satisfying (A2) in the paper is conditionally nonblocking if the $N$-modulo distance between any two outputs is not greater than two times of the $N$-modulo distance between the corresponding two inputs. Such a conditionally nonblocking property allows us to show that a twister network with $N$ inputs/outputs can be used as a $p \times p$ rotator and a $p \times p$ symmetric TDM switch for any $2 \le p \le N$. As such, one can use a twister network as the switch fabric for a two-stage load balanced switch that is capable of providing incremental update of the number of linecards.

Terminal reliability evaluation of the Augmented Data Vortex all optical interconnection network

Abstract: The Augmented Data Vortex switch has been proposed in our earlier publications as a high capacity, high throughput, and low-latency all optical packet switched interconnection network for optical switching that can overcome major challenges of all optical packet switching [1, 2]. Recently there has been much analysis and comparison of optical multistage interconnection networks (OMINs) from the aspect of reliability, the focus of this analysis being either terminal reliability (TR) or network reliability (NR). Since the ADV switch is based on a new topology, these issues need to be considered in addition to other performance factors such as latency, throughput, etc. In our earlier work we evaluated the fault tolerance and network reliability of ADV [1]. In this paper we present the terminal reliability evaluation of ADV.

On the performance of multistage cooperative networks

Abstract: We propose a decode-and-forward (DF) multistage cooperation protocol wherein the transmission between source and destination takes place in T ≥ 2 equal duration and orthogonal time phases with the help of relays. In the first time phase, the source broadcasts its message which is received by all potential relays. During subsequent time phases, the relays that have successfully decoded the message using information from all previous transmitting relays, transmit a space-time code for the source's message. The non-decoding relays keep accumulating information and transmit in the later stages when they are able to decode the message. This process continues for T cooperation stages. We develop an analytical expression for end-to-end outage probability which is valid for any number of stages and relays. We consider a relay placement scenario where relays are placed at equal intervals along the straight line between source and the destination. We investigate an interesting tradeoff between an increased SNR and decreased spectral efficiency as the number of cooperation stages is increased. It is also observed that the largest multistage cooperation gain is obtained in the low and moderate SNR regime.

Parallel Routing Algorithm for Extra Level Omega Networks on Reconfigurable Systems

Abstract: Several parallel routing algorithms have been proposed during the last three decades. However, most algorithms have been not implemented. Therefore, the execution time and memory resources have been neither measured nor reported. This work presents two parallel routing algorithms for Omega multistage networks by using hardware assistant approach. Both algoritms have been mapped on a FPGA. The first algorithm minimizes the execution time and it is based on a priority encoder. The second one otimizes the hardware resources by using embedded FPGA memories. Omega networks are blocking and some permutations are not completely routed. Extra levels increase the routing capability by doubling the number of paths. This work evaluates the route capacity as a function of network workload, parallel networks and extra levels. Network switches with 2 and 4 inputs/outputs have been taken into account. For each connection, the first algorithm spends only two clock cycles by using the priority encoder. For the second algorithm based on memories, the number of cycles per connection ranges from 2 to 10 and the average number of cycles is around 5.

Performance of Multistage Interconnection Networks for Multiprocessor Systems

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Design and Performance Estimation of Delta Networks for MPSOC on Programmable Circuits

Abstract: Multiprocessor systems on chip (MPSoC) designs are increasingly being used in today’s embedded system, to follow phenomenal increase of embedded products performance requirements In these systems one of the most critical components regarding overall efficiency is on-chip interconnections which have a great impact on the performance constraints of modern MPSOC Multistage interconnection networks have been frequently proposed as connection means in classical multiprocessor systems They are generally accepted concepts in the semiconductor industry for solving the problems related to on-chip communications This paper proposes the design and implementation of a flexible and scalable Delta network for MPSOC in an FPGA The configurable Delta MIN provides a variety of network topologies with the convenience of a manager for configuration

Fault tolerance analysis of Extended Pruned Vertically Stacked Optical Banyan networks with link failures and variable group size

Abstract: Vertically stacked optical banyan (VSOB) networks are attractive for serving as optical switching systems due to the good properties of banyan network structures (such as the small depth and self-routing capability), and it is expected that using the VSOB structure will lead to a better fault-tolerant capability because it is composed of multiple identical copies of banyan networks In the Extended Pruned Vertically Stacked Optical Banyan (EP-VSOB) network, the number of pruned planes has always been considered as √N, and a few extra planes (regular banyan) has been added with this pruned planes In this paper, we present the results of blocking analysis of EP-VSOB network incorporating link-failures in which the number of pruned planes can be 2x, where0≤x≥log 2 N, in addition to the variable extra planes This generalization helps us trade-off between different constraints and performance metrics Our simulation results show that for some given performance requirements (eg cost, speed or blocking probability), we can choose a network that has lower switch count compared to N - plane pruned crosstalk-free optical banyan networks Our result also reveals a fact that by accepting small link failure probability, the blocking behavior of EP-VSOB network is very similar to that of a fault-free one, which demonstrates our expectation of good fault-tolerant property of VSOB networks Simulation results also show that the blocking probability does not always increase with the increase of link-failures; blocking probability decreases for certain range of link-failures, and then increases again

Efficient Implementation of Symmetric Multistage Repackable Networks

Abstract: We revisited the problem of efficient implementation of large scale switching systems using repackable networks [16], which offer performance approaching that of strict sense nonblocking networks. In particular, we study repackable networks with more than three stages. Our method uses bypass path(s) for designing the repackable network to maintain path continuity while at repacking. This is essential if networks are not to be limited to time-slatted operations. We investigate the minimum number of bypass links required for different network sizes. The required minimum number of bypass links for a network depends on the number of links forming a rearrangement chain [2]. This paper shows minimum number of links required to complement a repackable and thereby demonstrate its attractive scaling properties. It also proposes some future applications where these network can be applicable.