Showing papers on "Operational amplifier published in 1982"

MOS operational amplifier design-a tutorial overview

Abstract: Presents an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level. Primary emphasis is placed on CMOS amplifiers because of their more widespread use. Factors affecting voltage gain, input noise, offsets, common mode and power supply rejection, power dissipation, and transient response are considered for the traditional bipolar-derived two-stage architecture. Alternative circuit approaches for optimization of particular performance aspects are summarized, and examples are given.

A family of differential NMOS analog circuits for a PCM codec filter chip

Abstract: A new NMOS PCM codec filter uses low-noise fully differential circuits to achieve supply rejection of 36 dB and idle channel noise of 6 dB/SUB rnc0/. The die size is 24 mm/SUP 2/ and the active standby power is 150 mW/5 mW.

A MOS switched-capacitor instrumentation amplifier

Abstract: Describes a precision switched-capacitor sampled-data instrumentation amplifier using NMOS polysilicon gate technology. It is intended for use as a sample-and-hold amplifier for low level signals in data acquisition systems. The use of double correlated sampling technique achieves high power supply rejection, low DC offset, and low 1/f noise voltage. Matched circuit components in a differential configuration minimize errors from switch channel charge injection. Very high common mode rejection (120 dB) is obtained by a new sampling technique which prevents the common mode signal from entering the amplifier. This amplifier achieves 1 mV typical input offset voltage, greater than 95 dB PSRR, 0.15 percent gain accuracy, 0.01 percent gain linearity, and an RMS input referred noise voltage of 30 /spl mu/V/input sample.

Analysis of the settling behavior of an operational amplifier

Abstract: The settling behavior of a pole-splitting compensated operational amplifier is analyzed using a second-order (two-pole) transfer function. It is shown that although the slewing period of the amplifier is well approximated by the commonly used formula for slew rate, the settling behavior after the slewing period can only be fully explained using a second-order transfer function. Simple criteria relating the circuit parameters to the damping ratio of a second-order feedback system are given. Analytical expressions for the amplifier responses and settling times are derived. The analysis is justified by close correspondence with computer simulations.

Switched capacitor AM modulator/demodulator

Abstract: A first embodiment of an integrable switched capacitor modulator comprises a differential input operational amplifier A1 having a virtual ground potential impressed on its inverting input terminal; capacitors C1, C2 and C3; and switch means operative for alternately (1) charging C1 with an input voltage while connecting C2 and C3 in series with A1 and across it, respectively, for causing it to produce an inverted version of the input voltage, and (2) discharging C2 and C3 while connecting the sample of the input voltage on C1 across A1 for causing it to output a non-inverted sample of the input voltage. The modulated output signal from A1 is preferably bandpass filtered to eliminate baseband spectral components fed through A1 when C2 is connected in series with the input terminal thereof. In a second embodiment which is insensitive to feedthrough and which requires only two capacitors C1 and C4, the switch means alternately (1) charges C1 with the input voltage while connecting a prior sample of the input voltage on C4 across A1 for causing it to output an inverted sample of the input voltage, and (2) charges C4 with the input signal while connecting the sample of the input voltage on C1across A1 in the opposite polarity for causing it to output a non-inverted sample of the input voltage. This embodiment has particular advantage as a demodulator since the built-in sample-and-hold function provides low pass filtering of the output signal of A1.

Touch type input device

Abstract: PURPOSE:To eliminate the undesired input and to improve the operability, by providing a pressure detector at the lower side of an input touch plate, comparing the touch pressure with the reference level and inhibiting an output when the touch pressure is lower than the reference level. CONSTITUTION:Piezoelectric converting elements 6a-6c are provided on a support plate 5 and at the lower side of a touch type input plate 1. These piezoelectric converting elements are connected to the negative terminal of operational amplifier 7 via resistances R1-R3. Thus a touch pressure detecting means 2 is obtained. The output of the amplifier 7 is fed to the positive terminal of a comparing means 3 and compared with the reference voltage of the negative terminal. When the output of the amplifier 7 is higher than the reference voltage, ''1'' is delivered and fed to an AND circuit 9. A signal corresponding to a touch point is fed to another input 10 of the circuit 9. Then the circuit 9 delivers an output only when the touch pressure is higher than the prescribed level. The reference voltage of the negative terminal controls a constant resistance VR of a level setting means 4 to set a desired level of touch pressure. As a result, an input due to an inadvertent contact is inhibited and the touch pressure is set at a desired level to improve the operability of a touch input device.

Gate-coupled field-effect transistor pair amplifier

Abstract: An enhancement mode (104, 204, 404) and a depletion mode (102, 202, 402) pair of N-channel MOS transistors have their drain-source conduction paths connected in series and provided with a bias current means (120, 220, 306, 410) The gates (106, 206, 308, 310) are coupled together as an input node In one embodiment (100) their bulk regions are source-connected and the output (118) is from the source of the enhancement mode device (104) to obtain a source follower configuration amplifier In a second embodiment (200), the output (218) is taken from the drain (208) of the depletion mode device (202) to obtain a common source configuration amplifier Two source follower pairs (302, 304) are disclosed connected in parallel to form a differential input voltage amplifier stage (300) A common source pair (402, 404) is disclosed in combination with an additional enhancement mode transistor (406) to form a current mirror (400)

New clock feedthrough cancellation technique for analogue MOS switched-capacitor circuits

Abstract: A new technique for minimising DC offsets caused by clock feedthrough in switched-capacitor circuits is presented. Unlike some techniques presented in the past, the clock feedthrough cancellation is dependent only on matching and the common mode rejection ratio of the op-amps. The technique is quite general and can be applied to most switched-capacitor circuits that use differential input op-amps.

Switched capacitor DSB modulator/demodulator

Abstract: An integrated single-sideband modulator comprises six integrated capacitors C1-C6 and first switch means alternately connecting C1 and C2 as feedback capacitors across a differential input operational amplifier A1. The amplifier has a virtual ground potential on its inverting input terminal for causing it to operate as a voltage source and render the circuit relatively insensitive to parasitic capacitance effects associated with capacitor plates. Second switch means cooperates with A1, C1 and C2 and is responsive to 4-phase clock signals for driving input capacitors C3-C6 so as to convert first and second quadrature-phase input signal voltages into first and second electrical charge flow signals on the inverting input terminal that are a function of products of representations of the first and second voltages in switch state time intervals and associated pulse trains which have a 90° phase difference therebetween and a repetitive pattern such as +1, +1, -1, -1, etc. The amplifier and feedback capacitors combine the charge signals for producing a single-sideband signal on A1's output terminal. This circuit is converted to a balanced modulator by omitting C5 and C6. In an alternate embodiment of a single sideband modulator that requires only a pair of switched capacitors C11 and C12, a 4-phase switch means alternately charges C11 and C12 with associated ones of the quadrature-phase input signal voltages while alternately connecting C12 and C11 as feedback capacitors across A1, the polarity of each capacitors feedback voltage being reversed each time that capacitor is connected across the amplifier. This circuit is operated as a balanced modulator by omitting one of the capacitors.

Polyphase PDM amplifier

Abstract: A polyphase PDM amplifier is disclosed including plural parallel PDM amplifier stages (10, 12, 14, 16), all amplifying the same input signal. The PDM amplifier outputs are combined to produce a combined amplifier output. The various PDM amplifier stages modulate PDM carrier signals of like frequencies but differing phases. Capacitors (40, 42, 44, 46) are connected from each amplifier output to a common circuit node (48). These capacitors reduce the amplitudes of the spurious, out-of-phase components in the amplifier outputs which are introduced by the PDM modulation-demodulation process.

Precision band-gap voltage reference circuit

Abstract: A band-gap voltage reference circuit which incorporates a band-gap differential amplifier supplied with constant, temperature-independent current, a high gain differential-to-single-ended converter, temperature-compensated negative feedback means and a common source of biasing to serve as a device to provide an output reference voltage so that the output reference voltage is precise and independent of variations in temperature, loading and power supply voltage. An improved amplifier is also disclosed.

Two loop automatic level control for power amplifier

Abstract: The power supply potential applied to the final stage of an RF amplifier isodulated by means of an adaptive power supply. The power supply potential applied to the final RF amplifier is controlled by a first control loop in accordance with an error signal derived from a comparison of a signal corresponding to the weighted sum of the magnitude of the supply voltage applied and the current drawn by the final amplifier and the amplitude of the modulating signal. Additionally, an automatic level control circuit controls the level of the RF output signal in a second control loop in accordance with a comparison between the magnitude of the RF output of the amplifier and the amplitude of the modulating signal.

Parasitic insensitive, biphase switched capacitor filters realized with one operational amplifier per pole pair

Abstract: Practical techniques are given for reducing the number of operational amplifiers (op-amps) in switched capacitor filters. Op-amp count is typically reduced to one op-amp per pole pair, while maintaining the insensitivity to top and bottom plate parasitics heretofore associated with one-op-amp-per-pole structures. These techniques are used to develop a parasitic insensitive single amplifier resonator and a general single amplifier biquad. Next, complete design procedures are given for these circuits. Finally, the same methods are applied to leapfrog structures, where similar op-amp savings are demonstrated.

Extending op amp capabilities by using a current- source power supply

Abstract: A technique for realizing a versatile operational floating amplifier by using a standard op amp is presented. Such a building block greatly extends op amp capabilities. Especially in cases where grounded loads have to be current driven and where accurate low-noise termination impedances must be realized, this technique may be very useful.

Transimpedance amplifier for optical receivers

Abstract: An improved transimpedance amplifier allows an optical transmitter and receiver to be in close proximity to each other without fear of overloading the receiver. The improvement increases the dynamic range of the transimpedance amplifier and thereby the operating range of the receiver. A peak detector (22) at the output of an inverting amplifier (11) within the transimpedance amplifier turns on a field effect transistor (FET) circuit (23) when an AC component of an electrical signal becomes so large that the inverting amplifier would otherwise go into saturation. The FET circuit (23) acts as an AC shunt impedance at the input of the inverting amplifier and diverts the excess AC current to ground (30). Also, the FET circuit (23) acts as a DC resistance in concert with sense and sink current mirrors (21) and (24) to effectively divert an excessive DC component of the electrical signal away from the input of the inverting amplifier (11). Although the dynamic range of the transimpedance amplifier is increased, the optical sensitivity and the performance of the receiver remain unchanged.

Offset compensation for switched capacitor integrators

Abstract: OFFSET COMPENSATION FOR SWITCHED CAPACITOR INTEGRATORS Roubik Gregorian Glenn Wegner ABSTRACT An integrator circuit utilizing an operational ampli-fier (19) and switched capacitor elements (11, 13 and 16) in place of resistors in such a manner as to provide compensation for voltage offsets present in the operational amplifier resulting in an output voltage (VOUT) free from the effects of voltage offsets inherent in operational amplifiers.

Manual muscle tester

Abstract: A portable manual muscle tester has an external actuator, a case capable of being held in one hand and a digital display indicating peak force applied to the actuator. Strain gages connected in a bridge circuit are located on a flexure contacted by the actuator. The flexure is a cantilever beam shaped to fit the small case and to prevent reflected or mounting stresses being registered in the force display. The circuit from the strain gage bridge to the display includes an instrumentation amplifier followed by a peak freeze circuit that includes operational amplifiers and a peak freeze capacitor. The peak freeze capacitor provides a voltage that is read by a digital volt meter. A further operational amplifier connected as an integrator feeds back from the peak freeze circuit to an input of the instrumentation amplifier to reset the meter to zero after the displayed force reading has been noted.

Alterable frequency response electrocardiographic amplifier

Abstract: An electrocardiographic amplifier having an integrator in the feedback loop between the amplifier's input and output whose time constant is varied by the duty cycle of a series switch to vary the low frequency 3 dB roll-off point as a function of the detected low frequency noise in the amplifier output signal. A capacitor is switched in parallel with the inverting feedback resistor to lower the high frequency 3 dB roll-off point in response to detected high frequency noise.

High speed AGC circuit

Abstract: An automatic gain control circuit is disclosed which enables the control of feedback gain to stabilize the circuit and increase its speed of operation The AGC circuit includes an operational amplifier having a varactor diode coupled between one input and an output The circuit is used to provide a feedback control signal in response to an output signal such that the varactor diode reduces loop gain when the output signal would otherwise cause an increase in gain and drive the feedback loop to instability, and increases loop gain when the output signal would otherwise cause a decrease in loop gain and lower response time

Amplifier with signal-dependent voltage supply source

Abstract: In a combination of an amplifier (2,5,6) and a signal-dependent voltage supply source (16-23) coupled thereto, a portion of the signal from a signal source (1) is applied by an amplifier (9) to a comparator (16), the output signal of which controls a limiter (20-21). A portion of the output signal thereof is applied as a feedback signal to a second input of the comparator (16) by means of a low-pass filter (22) and a feedback network (23) in series. The feedback loop thus formed is arranged so that it oscillates at a comparatively high frequency. A signal-dependent modulation of the pulse width and/or the pulse density then occurs at the limiter output. A supply voltage for the amplifier is derived from the output of the filter (22). Owing to the high feedback factor of the feedback loop at the signal frequencies the supply voltage can adequately follow the output signal of the amplifier independently of component tolerances and any load variations.

Monolithically integrable MOS-comparator circuit

Abstract: A circuit of a monolithically integrable MOS-comparator has a capacitor, a signal input and a reference input of the comparator being alternatingly connected to the capacitor via respective first and second clock-controlled transfer transistors, a first amplifier stage having a control input and an output, the capacitor being directly connected to the control input and being also connected via a third transfer transistor to the output of the first amplifier stage, a second amplifier stage having a control input and an output, the output of the first amplifier stage being further connected via a fourth transfer transistor to the control input of the second amplifier stage. A third amplifier stage identical with the first and second amplifier stages has a signal input and an output, the output of the second amplifier stage being a first signal output of the comparator and being also connected to the signal input of the third amplifier stage. The output of the third amplifier stage as a second signal output of the comparator and as connected via a fifth transfer transistor to the control input of the second amplifier stage. Means for transmitting two clock signals are connected to the first and second transfer transistors, respectively, for alternatingly switching the signal input and the reference input, respectively, of the comparator to the capacitor, the signal-transmitting means being also connected to the third, fourth and fifth transfer transistors for controlling the same.

Current source frequency compensation for a CMOS amplifier

Abstract: A CMOS linear amplifier is disclosed with a frequency compensation circuit that employs a Miller integrater construction in which the feedback capacitor is coupled by way of a noninverting amplifier operating at constant current and therefore does not load the inverting amplifier input or bypass the integrator amplifier.

Temperature stable CMOS voltage reference

Abstract: A voltage reference is developed by operating a pair of different threshold CMOS transistors as a differential linear amplifier with the reference voltage value determined as an input offset voltage. The differential amplifier consists of an input stage with controlled offset, a high gain inverter and an output stage which is directly coupled back to the inverting input. The circuit is biased up using a depletion transistor at zero bias and a current mirror configuration for supplying all stages.

Switched capacitor gain stage with offset and switch feedthrough cancellation scheme

Abstract: SWITCHED CAPACITOR GAIN STAGE WITH OFFSET AND SWITCH FEEDTHROUGH CANCELLATION SCHEME Gideon Amir Yusuf Haque Roubik Gregorian ABSTRACT An operational amplifier gain stage utilizing switched capacitor resistor equivalent circuits is designed utilizing a delayed clock reference signal (0D, ?D) in a unique manner, thereby eliminating the effects of spurious error voltages (Es) generated when utilizing metal oxide silicon field effect transistors as switches (12, 15, 21, 23, 25). The single remaining MOSFET switch (21) which will contribute a spurious voltage component to the output of the operational amplifier gain stage is designed in such a manner as to minimize the spurious voltage generated during operation of the MOSFET switch.A single dummy switch (31) is utilized to further minimize the spurious voltage generated by this single MOSFETswitch.

Antitrust and monopoly

Abstract: Contents: History of the Thermionic Valve Operation of the Electron Tube Wiring Tube Circuits CD/Line Amplifier Hi-Fi Amplifier General-Purpose Line Amplifier Pick-Up/Line Amplifier with SRPP Output Hi-Fi Output Amplifier with 2xEL34 Class A Stereo Output Amplifier with 2xKT88 Miscellaneous Amplifiers Guitar/Keyboard Amplifiers Guitar Amplifier with Transistor Input Voltage Regulation with Valves Heater-Voltage Supplies SRPP Amplifier for CD Players Track Layouts of PCBs.

Integrator design for high-frequency active filter applications

Abstract: The combined effects of deviation from ideal in integrator magnitude and phase on the performance of integrator-based active filters is investigated. The limitations of using the integrator Q -factor as a measure of integrator performance are discussed. Conditions for minimizing the operational amplifier gain bandwidth product effects on integrator-based active filters are established which are dependent only upon the characteristics of the integrators. Inverting and noninverting integrators for use in active filters which are independent of first-order and second-order operational amplifier time constant effects and require no amplifier matching are introduced. These new integrators are compared with existing actively compensated configurations directly and in a filter structure. Experimental results are presented which confirm the theoretical development.

Novel sampled-data MOS multiplier

Abstract: In many analogue systems, such as correlators, adaptive filters, curve-fitting etc., analogue multipliers are required. However, common MOS multipliers do not match the performance of bipolar ones. In the letter, a new one-quadrant multiplier concept suitable for MOS systems applications is presented. The method is based on time-division concept and its building blocks are well known MOS subcircuits such as comparators, operational amplifiers, and current sources. The properties of the system are demonstrated using computer simulations.

Hybrid models of 3-port immittance convertors and current and voltage conveyors

Abstract: New circuit realisations of two types of 3-port immittance convertors and, as a special case, a realisation of current and voltage conveyors, are presented using resistors and operational amplifiers.

Operational amplifier gain - bandwidth product effects on the performance of switched-capacitor networks

Abstract: A method of analyzing switched-capacitor (SC) filters which incorporates a single-pole model of the operational amplifiers (op amp's) is presented. Closed-form algebraic expressions for filter transfer functions in the z -domain are obtained which are computationally more efficient than time-domain methods. The necessity for including a frequency dependent model of the op amp rather than the common finite gain model in doing a performance analysis, especially when considering stability, is emphasized. To illustrate the method of analysis, an analog integrator, an analog second-order bandpass filter, and their SC counterparts are considered. The s -domain performance of the analog \footnote[1]{circuits} is compared with the z -domain performance of the sampled-data configurations to show how the finite gain-bandwidth product (GB) of the op amp's affects the respective topologies. These comparisons show that the effects of switching rates and switching arrangements on filter performance are strongly dependent upon the GB product of the op amps. These comparisons also emphasize the fact that it is not sufficient to investigate the effect of the operational amplifiers on the performance of an analog filter to predict the performance of a SC filter derived from the analog configuration.